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Preliminary Technical Data
FEATURES
Low power, low IF transceiver Frequency bands 80 MHz to 650 MHz 862 MHz to 940 MHz Modulation schemes 2FSK, 3FSK, 4FSK Spectral shaping Gaussian and raised-cosine filtering Data rates supported 0.05 kbps to 25 kbps 2.3 V to 3.6 V power supply Programmable output power -16 dBm to +13 dBm in 63 steps Automatic PA ramp control Receiver sensitivity -125 dBm at 1 kbps, 2 FSK On-chip VCO and fractional-N PLL
High Performance Narrowband ISM Transceiver IC ADF7021
On-chip 7-bit ADC and temperature sensor Fully automatic frequency control loop (AFC) Digital RSSI Integrated Tx/Rx switch Leakage current <1 A in power-down mode
APPLICATIONS
Narrow-band standards ETSI EN 300-220, FCC Part 90, FCC Part 15, FCC Part 95, ARIB STD-T67 Low cost, wireless data transfer Remote control/security systems Wireless metering Private mobile radio Wireless medical telemetry service (WMTS) Keyless entry Home automation Process and building control Pagers
FUNCTIONAL BLOCK DIAGRAM
RSET TEMP SENSOR CE CREG(1:4) MUXOUT MUX 7-BIT ADC
RLNA
POLARIZATION
LDO(1:4)
TEST MUX
LNA
RFIN RFINB GAIN
IF FILTER
RSSI/ OFFSET CORRECTION
2FSK 3FSK 4FSK DEMODULATOR
CLOCK AND DATA RECOVERY
DATA CLK | TxDATA Tx/Rx CONTROL DATA I/O | RxDATA SWD
AGC CONTROL SERIAL PORT
SLE SDATA SREAD SCLK
PA RAMP
AFC CONTROL
RFOUT
DIVIDERS/ MUXING
DIV P
N/N + 1
- MODULATOR
2FSK 3FSK 4FSK MOD CONTROL
GAUSSIAN/ RAISED COSINE FILTER
VCO MUX CP PFD
DIV R RING OSC CLK DIV
3FSK ENCODING
L1 L2
VCOIN
CPOUT
OSC1
OSC2
CLKOUT
Figure 1.
Rev. PrI
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05876-001
ADF7021 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Characteristics..................................................................... 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Frequency Synthesizer ................................................................... 12 Reference Input........................................................................... 12 MUXOUT.................................................................................... 13 Voltage Controlled Oscillator (VCO) ...................................... 14 Choosing Channels for Best System Performance................. 14 Transmitter ...................................................................................... 15 RF Output Stage.......................................................................... 15 Modulation Schemes.................................................................. 15 Spectral Shaping ......................................................................... 17 Modulation and Filtering Options ........................................... 17 Receiver Section.............................................................................. 18 RF Front End............................................................................... 18 RSSI/AGC.................................................................................... 19 FSK Demodulators on the ADF7021....................................... 19 FSK Correlator/Demodulator................................................... 19 Linear 2FSK Demodulator ........................................................ 21 3FSK Demodulator..................................................................... 21 4FSK Demodulator..................................................................... 21
Preliminary Technical Data
AFC Section ................................................................................ 21 Automatic Sync Word Recognition ......................................... 22 Applications..................................................................................... 23 LNA/PA Matching...................................................................... 23 Transmit Protocol and Coding Considerations ..................... 24 Device Programming after Initial Power-Up ........................... 24 Interfacing to Microcontroller/DSP ........................................ 26 Serial Interface ................................................................................ 27 Readback Format........................................................................ 27 Register 0--N Register............................................................... 28 Register 1--VCO/Oscillator Register ...................................... 29 Register 2--Transmit Modulation Register ............................ 30 Register 3--Transmit/Receive Clock Register........................ 31 Register 4--Demodulator Setup Register ............................... 32 Register 5--IF Filter Setup Register......................................... 33 Register 6--IF Fine Cal Setup Register ................................... 34 Register 7--Readback Setup Register...................................... 35 Register 8--Power Down Test Register................................... 36 Register 9--AGC Register......................................................... 37 Register 10--AFC Register ....................................................... 38 Register 11--Sync Word Detect Register................................ 39 Register 12--SWD/Threshold Setup Register........................ 40 Register 13--3FSK Demod Register ........................................ 41 Register 14--Test-DAC Register .............................................. 41 Register 15--Test Mode Register ............................................. 42 Outline Dimensions ....................................................................... 44 Ordering Guide .......................................................................... 44
Rev. PrI | Page 2 of 44
Preliminary Technical Data GENERAL DESCRIPTION
The ADF7021 is a low power, highly integrated 2FSK/3FSK/4FSK transceiver. It is designed to operate in the narrow-band, license-free ISM bands and licensed bands in the 80 MHz to 650 MHz and 862 MHz to 940 MHz frequency ranges. It has both Gaussian and raised cosine data filtering options to improve spectral efficiency for narrow-band applications. It is suitable for circuit applications targeted at European ETSI-EN 300-220, the Japanese ARIB STD-T67, the Chinese Short Range Device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021 very suitable for price-sensitive and area-sensitive applications. The transmit section contains a voltage controlled oscillator (VCO) and a low noise fractional-N PLL with output resolution of <1 ppm. This frequency-agile PLL allows the ADF7021 to be used in frequency hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from -16 dBm to +13 dBm and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.
ADF7021
A low IF architecture is used in the receiver (100 kHz), minimizing power consumption and the external component count while avoiding interference problems at low frequencies. The IF filter has programmable bandwidths of 12.5 kHz, 18.75 kHz, and 25 kHz. The ADF7021 supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range, allowing the PLL to track out the frequency error in the incoming signal. An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, and the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to 10C over the full operating temperature range of -40C to +85C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.
Rev. PrI | Page 3 of 44
ADF7021 SPECIFICATIONS
Preliminary Technical Data
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25C. All measurements are performed with the EVAL-ADF7021DBx using PN9 data sequence, unless otherwise noted. Table 1.
Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) Frequency Ranges (Divide-by-2 Mode) Frequency Ranges (Direct Output) Frequency Ranges (Divide-by-2 Mode) Phase Frequency Detector (PFD) Frequency TRANSMISSION PARAMETERS Data Rate Frequency Shift Keying Frequency Deviation1 Deviation Frequency Resolution Gaussian Filter BT Raised Cosine Filter Alpha Transmit Power 2 Transmit Power Variation vs. Temperature Transmit Power Variation vs. VDD Transmit Power Flatness Programmable Step Size -20 dBm to +13 dBm Spurious Emissions Integer Boundary Reference Harmonics Second Harmonic Third Harmonic All Other Harmonics Optimum PA Load Impedance3 Min 135 80 862 431 RF/256 Typ Max 650 325 940 470 TBD Unit MHz MHz MHz MHz MHz Test Conditions External VCO inductor External VCO inductor, divide-by-2 enabled Internal VCO inductor Internal VCO inductor, divide-by-2 enabled
0.05 56 306 56 0.5 0.5 -20 1 1 1 0.3125 -55 -65 -27 -21 -35 39 + j61 48 + j54 54 + j94
25
kbps Hz Hz Hz Phase frequency detector (PFD) = 3.625 MHz PFD = 20 MHz PFD = 3.625 MHz
+13
dBm dB dB dB dB dBc dBc dBc dBc dBc
VDD = 3.0 V, TA = 25C From -40C to +85C From 2.3 V to 3.6 V at 915 MHz, TA = 25C From 902 MHz to 928 MHz, 3 V, TA = 25C
50 kHz loop bandwidth (BW)
Unfiltered conductive Unfiltered conductive Unfiltered conductive FRF = 915 MHz FRF = 868 MHz FRF = 433 MHz Bit error rate (BER) = 10-3, FRF = 915 MHz, low noise amplifier (LNA) and power amplifier (PA) matched separately4 FDEV = 1 kHz, high sensitivity mode5 Pin = -20 dBm, 2 CW interferers FRF = 915 MHz, F1 = FRF + 3 MHz F2 = FRF + 6 MHz, maximum gain <1 GHz at antenna input >1 GHz at antenna input
RECEIVER PARAMETERS 2FSK Input Sensitivity
Sensitivity at 1 kbps LNA and Mixer, Input IP3 Enhanced Linearity Mode Low Current Mode High Sensitivity Mode Rx Spurious Emissions6 AFC Maximum Pull-In Range Response Time Accuracy
-125 6.8 -3.2 -35 -57 -47 127.5 48 1
dBm dBm dBm dBm dBm dBm kHz Bits kHz
Mod index = 0.875
Rev. PrI | Page 4 of 44
Preliminary Technical Data
Parameter CHANNEL FILTERING Adjacent Channel Rejection (Offset = 1 x IF Filter BW Setting) Second Adjacent Channel Rejection (Offset = 2 x IF Filter BW Setting) Third Adjacent Channel Rejection (Offset = 3 x IF Filter BW Setting) Image Channel Rejection Co-Channel Rejection Wideband Interference Rejection BLOCKING 1 MHz 5 MHz 10 MHz 10 MHz (High Linearity Mode) Saturation (Maximum Input Level) LNA Input Impedance Min Typ 27 50 55 35 -3 70 Max Unit dB dB dB dB dB dB Test Conditions
ADF7021
IF filter BW setting = 12.5 kHz, 18.75 kHz, 25 kHz Desired signal 3 dB above the input sensitivity level, CW interferer power level Increased until BER = 10-3, image channel excluded Image at FRF - 200 kHz Swept from 100 MHz to 2 GHz, measured as channel rejection Desired signal 3 dB above the input sensitivity level, CW interferer power level Increased until BER = 10-2
60 68 65 72 12 24 - j60 26 - j63 71 - j128 -110 to -36 2 3 150 65 130 65 -99 -113 128 40
dB dB dB dB dBm dBm dB dB s MHz/V MHz/V MHz/V dBc/Hz dBc/Hz Hz s
FSK mode, BER = 10-3 FRF = 915 MHz, RFIN to GND FRF = 868 MHz FRF = 433 MHz
RECEIVE SIGNAL STRENGTH INDICATOR (RSSI) Range at Input Linearity Absolute Accuracy Response Time PHASE-LOCKED LOOP (PLL) VCO Gain
See the RSSI/AGC section 902 MHz to 928 MHz band, VCO adjust = 0, VCO_BIAS_SETTING = 8 860 MHz to 870 MHz band, VCO adjust = 0 433 MHz, VCO adjust = 0 PA = 10 dBm, VDD = 3.0 V, PFD = 24.57 MHz, FRF = 433 MHz, VCO_BIAS_SETTING = 15 1 MHz offset From 200 Hz to 20 kHz, FRF = 868 MHz Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, loop bandwidth (LBW) = 50 kHz
Phase Noise (In-Band) Phase Noise (Out-of-Band) Residual FM PLL Settling
REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time Input Level ADC PARAMETERS INL DNL TIMING INFORMATION Chip Enabled to Regulator Ready Chip Enabled to RSSI Ready Tx to Rx Turnaround Time
3.625 3.625 33 2.1
TBD TBD
MHz MHz pF ms CMOS levels LSB LSB s ms
PC board layout and crystal specific 11.0592 MHz crystal, using 33 pF load capacitors See the Reference Input section
1 1 10 3.0 150 s + (5 x TBIT)
From 2.3 V to 3.6 V, TA = 25C From 2.3 V to 3.6 V, TA = 25C CREG = 100 nF See Table 14 for more details Time to synchronized data out, includes AGC settling; see AGC Information and Timing section for more details
Rev. PrI | Page 5 of 44
ADF7021
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN Control Clock Input LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall CLKOUT Load TEMPERATURE RANGE (TA) POWER SUPPLIES Voltage Supply VDD Transmit Current Consumption 0 dBm 10 dBm 0 dBm 10 dBm Receive Current Consumption Low Current Mode High Sensitivity Mode Power-Down Mode Low Power Sleep Mode
1 2 3
Preliminary Technical Data
Min 0.7 x V DD 0.2 x VDD 1 10 50 DVDD - 0.4 0.4 5 10 +85 Typ Max Unit V V A pF MHz V V ns pF C IOH = 500 A IOL = 500 A Test Conditions
-40
2.3 12.7 21 19.3 28 20 22 0.1
3.6
V mA mA mA mA mA mA
All VDD pins must be tied together VDD = 3.0 V, PA is matched into 50 FRF = 460 MHz FRF = 460 MHz FRF = 868 MHz FRF = 868 MHz
1
A
For definition of frequency deviation, see the Register 2--Transmit Modulation Register section. Measured as maximum unmodulated power. Output power varies with both supply and temperature. For matching details, see the LNA/PA Matching section. 4 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. 5 See Table 8 for a description of different receiver modes. 6 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
Rev. PrI | Page 6 of 44
Preliminary Technical Data TIMING CHARACTERISTICS
VDD = 3 V 10%, VGND = 0 V, TA = 25C, unless otherwise noted. Guaranteed by design, but not production tested. Table 2.
Parameter t1 t2 t3 t4 t5 t6 t8 t9 t10 Limit at TMIN to TMAX <10 <10 <25 <25 <10 <20 <25 <25 <10 Unit ns ns ns ns ns ns ns ns ns Test Conditions/Comments SDATA to SCLK setup time SDATA to SCLK hold time SCLK high duration SCLK low duration SCLK to SLE setup time SLE pulse width SCLK to SREAD data valid, readback SREAD hold time after SCLK, readback SCLK to SLE disable time, readback
ADF7021
t3
SCLK
t4
t1
t2
DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
SDATA
DB31 (MSB)
DB30
DB2
t6
SLE
t5
Figure 2. Serial Interface Timing Diagram
t1
SCLK
t2
SDATA REG7 DB0 (CONTROL BIT C1) SLE
t3
t10
X RV16 RV15 RV2 RV1
SREAD
t8
t9
Figure 3. Readback Timing Diagram
Rev. PrI | Page 7 of 44
05876-003
05876-002
ADF7021
1 x DATA RATE/32 RxCLK 1/DATA RATE
Preliminary Technical Data
Figure 4. RxData/RxCLK Timing Diagram
1/DATA RATE TxCLK
TxDATA
DATA
05876-005
FETCH
SAMPLE
Figure 5. TxData/TxCLK Timing Diagram
Rev. PrI | Page 8 of 44
05876-004
RxDATA
DATA
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND1 Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MLF JA Thermal Impedance Reflow Soldering Peak Temperature Time-at-Peak Temperature
1
ADF7021
Rating -0.3 V to +5 V -0.3 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -40C to +85C -65C to +125C 150C 26C/W 260C 40 sec
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly.
ESD CAUTION
GND = CPGND = RFGND = DGND = AGND = 0 V.
Rev. PrI | Page 9 of 44
ADF7021 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
Preliminary Technical Data
MUXOUT
CPOUT
CREG3
CVCO
GND1
OSC1
VCOIN CREG1 VDD1 RFOUT RFGND RFIN RFINB RLNA VDD4
1 2 3 4 5 6 7 8 9
PIN 1 INDICATOR
OSC2
VDD3
GND
VDD
L1
L2
36 35 34 33
CLKOUT DATA CLK | TxDATA DATA I/O | RxDATA SWD VDD2 CREG2 ADCIN GND2 SCLK SREAD SDATA SLE
ADF7021
TOP VIEW (Not to Scale)
32 31 30 29 28 27 26 25
RSET 10 CREG4 11 GND4 12
MIX_I 13 MIX_I 14 MIX_Q 15 MIX_Q 16 FILT_I 17 FILT_I 18 GND4 19 FILT_Q 20 FILT_Q 21 GND4 22 TEST_A 23 CE 24
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 Mnemonic VCOIN CREG1 VDD1 RFOUT Function The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. Regulator Voltage for PA Block. A 100 nF in parallel should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for PA Block. Decoupling capacitors of 0.1 F and 100 pF should be placed as close as possible to this pin. All VDD pins should be tied together. The modulated signal is available at this pin. Output power levels are from -16 dBm to +13 dBm. The output should be impedance matched to the desired load using suitable components. See the Transmitter section. Ground for Output Stage of Transmitter. All GND pins should be tied together. LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. See the LNA/PA Matching section. Complementary LNA Input. See the LNA/PA Matching section. External Bias Resistor for LNA. Optimum resistor is 1.1 k with 5% tolerance. Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 k with 5% tolerance. Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Chip Enable. Bringing CE low puts the ADF7021 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches. A latch is selected using the control bits. Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high impedance CMOS input. Serial Data Output. This pin is used to feed readback data from the ADF7021 to the microcontroller. The SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.
5 6 7 8 9 10 11 12 13 to 18 19, 22 20, 21, 23 24 25 26 27
RFGND RFIN RFINB RLNA VDD4 RSET CREG4 GND4 MIX_I, MIX_I, MIX_Q, MIX_Q, FILT_I, FILT_I, GND4 FILT_Q, FILT_Q, TEST_A CE SLE SDATA SREAD
Rev. PrI | Page 10 of 44
05876-006
Preliminary Technical Data
Pin No. 28 29 30 31 32 33 Mnemonic SCLK GND2 ADCIN CREG2 VDD2 SWD
ADF7021
34
DATA I/O | RxDATA
35
DATA CLK | TxDATA
36 37
CLKOUT MUXOUT
38 39 40 41 42 43 44, 46 45, 47 48
OSC2 OSC1 VDD3 CREG3 CPOUT VDD L2, L1 GND, GND1 CVCO
Function Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input. Ground for Digital Section. Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin. Regulator Voltage for Digital Block. A 100 nF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin. Sync Word Detect. The ADF7021 asserts this pin when it has found a match for the sync word sequence (See the Register 11--Sync Word Detect Register section). This provides an interrupt for an external microcontroller indicating valid data is being received. Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply. In UART mode, this pin provides an output for the received data in receive mode. In transmit mode, this pin is high impedance (see the Register 0--N Register section). Outputs the data clock in both receive and transmit modes. This is a digital pin and normal CMOS levels apply. The positive clock edge is matched to the center of the received data. In transmit mode, this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. In UART mode, this pin is used to input the transmit data in transmit mode. In receive mode, this pin is high impedance (see the Register 0--N Register section). A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio. Provides the Lock_Detect Signal. This signal is used to determine if the PLL is locked to the correct frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface regulator (see the Register 0--N Register section). The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator. The reference crystal should be connected between this pin and OSC2. Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 10 nF capacitor. Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 10 nF capacitor. External VCO Inductor Pins. If using an external VCO inductor, a chip inductor should be connected across these pins to set the VCO operating frequency. If using the internal VCO inductor, these pins can be left floating. See the Voltage Controlled Oscillator (VCO) section for more information. Grounds for VCO Block. A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise.
Rev. PrI | Page 11 of 44
ADF7021 FREQUENCY SYNTHESIZER
REFERENCE INPUT
The on-board crystal oscillator circuitry (see Figure 7) can use an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected by using the automatic frequency control feature or by adjusting the fractional-N value (see the N Counter section). A single-ended reference (TCXO, CXO) can also be used. The CMOS levels should be applied to OSC2 with R1_DB12 set low.
Preliminary Technical Data
R Counter
The 3-bit R counter divides the reference input frequency by an integer from 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in Register 1. Maximizing the PFD frequency reduces the N value. This reduces the noise multiplied at a rate of 20 log(N) to the output and reduces occurrences of spurious components. Register 1 defaults to R = 1 on power-up: PFD [Hz] = XTAL/R
Loop Filter
The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop filter design is shown in Figure 9.
OSC1
CP2
OSC2
CP1
05876-007
Figure 7. Oscillator Circuit on the ADF7021
Two parallel resonant capacitors are required for oscillation at the correct frequency. Their values are dependent upon the crystal specification. They should be chosen to make sure that the series value of capacitance added to the PCB track capacitance adds up to the load capacitance of the crystal, usually 18 pF to 20 pF. Track capacitance values vary from 2 pF to 5 pF, depending on board layout. When possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions.
CHARGE PUMP OUT
VCO
05876-010
Figure 9. Typical Loop Filter Configuration
The loop should be designed so that the loop bandwidth (LBW) is approximately three times the data rate. Widening the LBW excessively reduces the time spent jumping between frequencies, but can cause insufficient spurious attenuation. Narrow-loop bandwidths can result in the loop taking long periods of time to attain lock. Careful design of the loop filter is critical to obtain accurate modulation. When using the Gaussian or raised cosine data filtering options, it is recommended to use a LBW of 2.0 to 2.5 times the data rate to ensure that sufficient samples of the input data are taken while filtering system noise. The free design tool ADIsimPLL can be used to design loop filters for the ADF7021.
Programmable Crystal Bias Current
Bias current in the oscillator circuit can be configured between 20 A and 35 A by writing to Bits R1_DB[13:14].
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the oscillator section, shown in Figure 7, and supplies a divideddown 50:50 mark-space signal to the CLKOUT pin. An even divide from 2 to 30 is available. This divide number is set in R1_DB[7:10]. On power-up, the CLKOUT defaults to divide-by-8.
DVDD CLKOUT ENABLE BIT
N Counter
The feedback divider in the ADF7021 PLL consists of an 8-bit integer counter and a 15-bit - fractional-N divider. The integer counter is the standard pulse-swallow type common in PLLs. This sets the minimum integer divide value to 23. The fractional divide value gives very fine resolution at the output, where the output frequency of the PLL is calculated as
OSC1
05876-008
DIVIDER 1 TO 15
/2
CLKOUT
Figure 8. CLKOUT Stage
FOUT =
Fractional - N XTAL x Integer _ N + R 215
To disable CLKOUT, set the divide number to 0. The output buffer can drive up to a 20 pF load with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A small series resistor (50 ) can be used to slow the clock edges to reduce these spurs at FCLK.
When VCO divide-by-2 (see the Voltage Controlled Oscillator (VCO) section) is selected, this formula becomes:
FOUT =
XTAL Fractional - N x 0.5 x Integer_N + R 215
Rev. PrI | Page 12 of 44
Preliminary Technical Data
REFERENCE IN 4\R PFD/ CHARGE PUMP VCO
ADF7021
regulator, the regulator must be at its nominal voltage before the ADF7021 can be programmed. The status of the regulator can be monitored at MUXOUT. When the regulator ready signal on MUXOUT is high, programming of the ADF7021 can begin.
DVDD
4\N THIRD-ORDER - MODULATOR
05876-011
REGULATOR READY (DEFAULT) FILTER CAL COMPLETE DIGITAL LOCK DETECT RSSI READY Tx_Rx LOGIC ZERO TRISTATE LOGIC ONE
05876-009
FRACTIONAL-N
INTEGER-N
Figure 10. Fractional-N PLL
MUX
CONTROL
MUXOUT
The combination of the integer-N (maximum = 255) and the fractional-N (maximum = 32768/32768) give a maximum N divider of 255 + 1. Therefore, the minimum usable PFD is
PFD MIN [Hz ] =
Maximum Required Output Frequency
(255 + 1)
Figure 11. MUXOUT Circuit
DGND
For example, when operating in the European 868 MHz to 870 MHz band, PFDMIN equals 3.4 MHz.
Filter Cal Complete
MUXOUT can be set to filter cal complete, which is active high. This indicates when a fine filter calibration has been completed. It can be used as an interrupt to a microcontroller.
Voltage Regulators
The ADF7021 contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Each regulator should have a 100 nF capacitor connected between CREG and GND. When CE is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 mA. Bringing the CE pin low disables the regulators, reduces the supply current to less than 1 A, and erases all values held in the registers. The serial interface operates from a regulator supply; therefore, to write to the part, the user must have CE high and the regulator voltage must be stabilized. Regulator status (CREG4) can be monitored using the regulator ready signal from muxout.
Digital Lock Detect
Digital lock detect indicates when the PLL has locked. The lock detect circuit is located at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until a 25 ns phase error is detected at the PFD.
RSSI Ready
MUXOUT can be set to RSSI ready. This indicates that the internal analog RSSI has settled and a digital RSSI readback can be performed.
MUXOUT
The MUXOUT pin allows the user to access various digital points in the ADF7021. The state of MUXOUT is controlled by Bits R0_DB[29:31].
TX_RX
TX_RX signifies whether the ADF7021 is in transmit or receive mode. When in transmit ,mode, this signal is low. When in receive mode, this signal is high. It can be used to control an external Tx/Rx switch.
Regulator Ready
Regulator ready is the default setting on MUXOUT after the transceiver is powered up. The power-up time of the regulator is typically 50 s. Because the serial interface is powered from the
Rev. PrI | Page 13 of 44
ADF7021
VOLTAGE CONTROLLED OSCILLATOR (VCO)
To minimize spurious emissions, the on-chip VCO operates from 1724 MHz to 1880 MHz. The VCO signal is then divided by 2 to give the required frequency for the transmitter and the required LO frequency for the receiver. The VCO should be recentered, depending on the required frequency of operation, by programming the VCO adjust bits R1_DB[23:24]. The VCO is enabled by Bit R1_DB17. A further frequency divide-by-2 is included after the PLL to allow operation from 432 MHz to 470 MHz using the internal VCO inductor and 80 MHz to 325 MHz using the external VCO inductor. This divide-by-2 is enabled by setting R1_DB18 to 1. The VCO needs an external 22 nF capacitor between the VCO and the regulator to reduce internal noise.
VCO BIAS R1_DB(19:22) LOOP FILTER
Preliminary Technical Data
Using the External VCO Inductor
When using an external inductor, the center frequency of the VCO is set by the internal varactor capacitance and the combined inductance of the external chip inductor, bond wire, and PCB track. A plot of the VCO operating frequency vs. total external inductance (chip inductor + PCB track) is shown in Figure 13. The inductance for a PCB track using FR4 material is approximately 0.57 nH/mm. This should be subtracted from the total value to determine the correct chip inductor value.
750 700 650
FREQUENCY (MHz)
600 550 500 450 400 350
FMAX (MHz)
VCO
/2 /2
MUX
TO PA
300 250
05876-012
220F CVCO PIN TO N DIVIDER DIVIDE BY 2 R1_DB18
200
0
5
10
15
20
25
30
TOTAL EXTERNAL INDUCTANCE (nH)
Figure 12. Voltage Controlled Oscillator (VCO)
Figure 13. VCO Operating Frequency vs. Total External Inductance
The ADF7021 on-chip VCO can use either an internal or external tank inductor. The possible frequency ranges are given in Table 5.
Table 5. RF Output Frequency Ranges for Internal/External VCO Inductor and Divide-by-2 Enabled/Disabled
RF Frequency Output (MHz) 862 to 940 431 to 470 135 to 650 80 to 325 Int/Ext VCO Inductor R1_DB25 0 0 1 1 Divide-by-2 R1_DB18 0 1 0 1
VCO bias current can be adjusted using Bits R1_DB[19:22]. To minimize current consumption and to ensure reliable operation, the bias current setting should be as indicated in Table 6.
Table 6. Recommended VCO Bias Currents for External VCO Inductor
RF Frequency Output (f) f < 200 MHz 200 MHz < f < 450 MHz f > 450 MHz VCO Bias R1_DB[19:22] 0001 0010 0011
Internal VCO Inductor
To select the internal VCO inductor, set R1_DB25 to Logic 0, which is the default setting. VCO bias current can be adjusted using Bits R1_DB[19:22]. To ensure VCO oscillation, the minimum bias current setting under all conditions when using the internal VCO inductor is 0xA. The VCO should be recentered, depending on the required frequency of operation, by programming the VCO adjust bits R1_DB[23:24].
CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE
The architecture of fractional-N results in some level of the nearest integer channel moving through the loop to the RF output. These beat-note spurs are not attenuated by the loop, if the desired RF channel and the nearest integer channel are separated by a frequency of less than the LBW. The occurrence of beat-note spurs is rare because the integer frequencies are at multiples of the reference, which is typically >10 MHz. Beatnote spurs can be significantly reduced in amplitude by avoiding very small or very large values in the fractional register using the frequency doubler.
Rev. PrI | Page 14 of 44
05669-024
FMIN (MHz)
Preliminary Technical Data TRANSMITTER
RF OUTPUT STAGE
The power amplifier (PA) of the ADF7021 is based on a singleended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 load at a maximum frequency of 940 MHz. The PA output current and, consequently, the output power are programmable over a wide range. The PA configuration is shown in Figure 14. The output power is set using Bits R2_DB[13:18].
R2_DB(11:12) 2 IDAC 6 R2_DB(13:18)
ADF7021
If the PA is enabled/disabled by the PA_ENABLE bit in Register 2 (R2_DB7) it ramps up at the programmed rate but turns hard off. If the PA is enabled/disabled by the TX_RX bit in Register 0 (R0_DB27), it ramps up and down at the programmed rate.
1 DATA BITS 2 3 4 ... 8 ... 16
PA RAMP 0 (NO RAMP) PA RAMP 1 (256 CODES/BIT) PA RAMP 2 (128 CODES/BIT) PA RAMP 3 (64 CODES/BIT) PA RAMP 4 (32 CODES/BIT) PA RAMP 5 (16 CODES/BIT) PA RAMP 6 (8 CODES/BIT)
RFOUT +
R2_DB7 R0_DB27
05876-013
FROM VCO
PA RAMP 7 (4 CODES/BIT)
Figure 14. PA Configuration in FSK/GFSK Mode
Figure 15. PA Ramping Settings
The PA is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. Depending on the application, users can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of different antennas, such as loop or mono-pole antennas. See the LNA/PA Matching section for details.
PA Bias Currents
Control Bits R2_DB[11:12] facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of 7 A is recommended. If output power of greater than 10 dBm is required, a PA bias setting of 11 A is recommended. The output stage is powered down by resetting Bit R2_DB7.
PA Ramping
When the PA is switched on or off quickly, its changing input impedance momentarily disturbs the VCO output frequency. This process is called VCO pulling, and it manifests as spectral splatter, or spurs in the output spectrum around the desired carrier frequency. Some radio emissions regulations now place limits on these PA transient-induced spurs (for example, ETSI EN 300-220). By gradually ramping the PA on and off, PA transient spurs can be minimized. The ADF7021 has built-in PA ramping configurability. As Figure 15 illustrates, there are eight ramp rate settings, defined as a certain number of PA setting codes per one data-bit period. The PA steps through each of its 64 code levels, but at different speeds for each setting. The ramp rate is set by configuring Bits R2_DB[8:10].
MODULATION SCHEMES
In all modulation schemes, an accurate clock is provided on the DATA_CLK pin to latch the data from the microcontroller into the transmit section at the exact required data rate. The exact frequency of this clock is defined by:
DATA _ CLK = XTAL DEMOD _ DIVIDER x CDR _ DIVIDER x 32
where: XTAL is the crystal frequency. DEMOD_DIVIDER is the divider that sets the demod-clock rate (R3_DB[6:9]). CDR_DIVIDER is the divider that sets the CDR clock rate (R3_DB[10:17]).
Rev. PrI | Page 15 of 44
05876-014
RFGND
ADF7021
Binary Frequency Shift Keying (2FSK)
Two-level frequency shift keying is implemented by setting the N value for the center frequency and then toggling it with the TxDATA line. The deviation from the center frequency is set using Bits R2_DB[19:27]. The deviation from the center frequency in Hz is: Direct RF output:
PFD x TX _ FREQUENCY _ DEVIATION FSK DEVIATION [Hz] = 2 16 Divide-by-2 enabled:
Preliminary Technical Data
shaping is P(D) = 1 - D2. A precoder with transfer function 1/P(D) is used to undo the encoding process of the convolutional code P(D) at the transmitter side.
Tx DATA 0, 1
PRECODER 1/P(D)
0, 1
CONVOLUTIONAL ENCODER P(D)
0, +1, -1 FC FC + FDEV FSK MOD FC - FDEV CONTROL AND DATA FILTERING
FSK DEVIATION [Hz ] = 0.5 x PFD x TX _ FREQUENCY _ DEVIATION 2 16 where: TX_FREQUENCY_DEVIATION is a number from 1 to 511 (R2_DB[19:27]).
Figure 17. 3FSK Encoding
The signal map of one-zero binary data to the 3-level convolutional output follows. The convolutional encoder restricts the maximum number of sequential +1's or -1's to two and also delivers an equal number of +1's and -1's to the FSK modulator, thus ensuring equal spectral energy in both 3FSK sidebands.
3-Level Signal Mapping of the Convolutional Encoder
Tx DATA Precoder O/P Encoder O/P 1 1 +1 0 0 0 1 0 -1 1 1 +1 0 0 0 0 1 0 1 1 +1 0 1 0 0 1 0 1 0 -1
4R
PFD/ CHARGE PUMP
PA STAGE VCO
FSK DEVIATION FREQUENCY /N -FDEV +FDEV TxDATA FRACTIONAL-N INTEGER-N THIRD-ORDER - MODULATOR
05876-015
3FSK is selected by setting bits in R2_DB[4:6]. It can also be used with raised cosine filtering to further increase the spectral efficiency of the transmit signal.
Four-Level Frequency Shift Keying (4FSK)
Four-level frequency shift keying differs from binary FSK in that four possible frequencies are used to represent each pair of data bits to be transmitted instead of two possible frequencies for each bit of data. This halves the symbol rate because a frequency change is only required after every second bit. It also doubles the number of symbols because there are four possible arrangements of a pair of consecutive NRZ data bits. By minimizing the separation between symbol frequencies, 4FSK can have high spectral efficiency.
Tx DATA 0 0 0 1 1 0 1 1
Figure 16. 2FSK Implementation
Three-Level Frequency Shift Keying (3FSK)
In three-level FSK modulation (also known as ternary FSK), the binary data (Logic 0 and Logic 1) is mapped onto three distinct frequencies:
* * *
the carrier frequency (FC), the carrier frequency minus a deviation frequency (FC - FDEV), and the carrier frequency plus the deviation frequency (FC + FDEV).
F +3FDEV
A Logic 0 is mapped to the carrier frequency while a Logic 1 is either mapped onto frequency FC - FDEV or FC + FDEV. The bits to frequency mapping result in a reduced transmission bandwidth as energy is removed from the sidebands and transferred to the carrier frequency. This increases the spectral efficiency in comparison to 2FSK. To ensure there is no loss in SNR at the receiver due to the ternary nature of the modulation, a simple convolutional encoder is used. A block diagram of the transmit hardware used to realize this system is shown in Figure 17. The convolutional encoder polynomial used to implement the transmit spectral
SYMBOL FREQUENCIES
+FDEV
-FDEV
t
Figure 18. 4FSK Encoding
Oversampled 2FSK
In oversampled 2FSK, the data is sampled at 32 times the programmed rate, allowing odd data rates.
Rev. PrI | Page 16 of 44
05876-016
-3FDEV
05876-046
TO N DIVIDER
Preliminary Technical Data
SPECTRAL SHAPING
Gaussian or raised cosine filtering can be used to improve transmit spectral efficiency. The ADF7021 supports Gaussian filtering (BT = 0.5) on 2FSK modulation. Raised cosine filtering (alpha = 0.5) can be used with 2FSK, 3FSK, or 4FSK modulation.
ADF7021
MODULATION AND FILTERING OPTIONS
The various modulation and data filtering options are described in Table 7.
Table 7. Modulation and Filtering Options on the ADF7021
Modulation 2FSK Data Filtering None Gaussian Raised cosine None Raised cosine None Raised cosine None R2_DB[4:6] 000 001 101 010 110 011 111 100
Gaussian Frequency Shift Keying (GFSK)
Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the transmit data. The bandwidth time (BT) product of the Gaussian filter used is 0.5. Gaussian filtering can just be used with 2FSK modulation. This is selected by setting Bits R2_DB[4:6] to 001.
3FSK 4FSK Oversampled 2FSK
Raised Cosine Filtering
Raised cosine filtering provides digital prefiltering of the transmit data using a rasied cosine filter with a roll-off factor (alpha) of 0.5. Rasied cosine filtering can be used with 2FSK, 3FSK, and 4FSK. Raised cosine filtering is enabled by setting Bits R2_DB[4:6] as outlined in Table 7.
Rev. PrI | Page 17 of 44
ADF7021 RECEIVER SECTION
RF FRONT END
The ADF7021 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from powerline-induced interference problems. Figure 19 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption against each other in the way best suited for their applications. To achieve a high level of resilience against spurious reception, the low noise amplifier (LNA) features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (R0_DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Rx/Tx switch. See the LNA/PA Matching section for details on the design of the matching network.
I (TO FILTER) RFIN Tx/Rx SELECT [R0_DB27] RFINB LNA MODE [R9_DB25] LNA CURRENT [R9_DB(26:27)] LNA GAIN [R9_DB(20:21)] LNA/MIXER ENABLE [R8_DB6] SW2 LNA LO Q (TO FILTER) MIXER LINEARITY [R9_DB28]
Preliminary Technical Data
Based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust control bits LNA mode (R9_DB25) and mixer linearity (R9_DB28) as outlined in Table 8. The gain of the LNA is configured by the LNA gain field, R9_DB[20:21], and can be set by either the user or the automatic gain control (AGC) logic.
IF Filter Settings
Out-of-band interference is rejected by means of a fifth-order Butterworth polyphase IF filter centered on a frequency of 100 kHz. The bandwidth of the IF filter can be programmed between 12.5 kHz and 25 kHz by Control Bits R4_DB[30:31], and should be chosen as a compromise between interference rejection, attenuation of the desired signal, and the AFC pull-in range.
Coarse/Fine Filter Calibration
To compensate for manufacturing tolerances, the IF filter should be calibrated once after power-up. Coarse and fine calibration schemes are provided in order to offer a choice between fast calibration with the coarse scheme and high filter centering accuracy with fine calibration. Coarse calibration is enabled by setting Bit R5_DB4 high. Fine calibration is enabled by setting Bit R6_DB4 high. It is necessary to do a coarse calibration before doing a fine calibration. If the IF_FINE_CAL bit, R6_DB4, has already been configured high, it is possible to do a fine calibration by writing only to Register 5. Once initiated by writing to the part, the calibration is performed automatically without any user intervention. Calibration time is 200 s for coarse calibration and a few milliseconds for fine calibration, during which the ADF7021 should not be accessed. The IF filter calibration logic requires that the IF filter divider in Bits R5_DB[5:13] be set depending on the crystal frequency. It is important not to initiate the calibration cycle before the crystal oscillator has fully settled. If the AGC loop is disabled, the gain of IF filter can be set to three levels using the Filter Gain Field, R9_DB[22:23]. The filter gain is adjusted automatically if the AGC loop is enabled.
Figure 19. ADF7021 RF Front End
The LNA is followed by a quadrature downconversion mixer, which converts the RF signal to the IF frequency of 100 kHz. An important consideration is that the output frequency of the synthesizer must be programmed to a value 100 kHz below the center frequency of the received channel. The LNA has two basic operating modes: high gain/low noise mode and low gain/low power mode. To switch between these two modes, use the LNA Mode Bit, R9_DB25. The mixer is also configurable between a low current and an enhanced linearity mode using the Mixer Linearity Bit, R9_DB28.
Table 8. LNA/Mixer Modes
LNA Mode (R9_DB25) 0 1 1 1 1 0 LNA Gain Value (R9_DB[20:21]) 30 10 3 3 10 30
05876-017
Receiver Mode High Sensitivity Mode (default) Rx Mode2 Low Current Mode Enhanced Linearity Mode Rx Mode5 Rx Mode6
Mixer Linearity (R9_DB28) 0 0 0 1 1 1
Sensitivity (DR = 9.6 kbps, FDEV = 4.8 kHz) -117 TBD TBD TBD TBD TBD
Rx Current Consumption (mA) 22 20 19 19 20 21
Input IP3 (dBm) TBD TBD TBD TBD TBD TBD
Rev. PrI | Page 18 of 44
Preliminary Technical Data
RSSI/AGC
The RSSI is implemented as a successive compression log amp following the base band channel filtering. The log amp achieves 3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. Offset correction is achieved using a switched capacitor integrator in feedback around the log amp. This uses the BB offset clock divide. The RSSI level is converted for user readback and digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm.
OFFSET CORRECTION 1 A A A LATCH FSK DEMOD
ADF7021
where: AGC Settling = AGC_Wait_Time x Number of Gain Changes Thus, in the worst-case scenario, if the AGC loop has to go through all five gain changes, AGC_Delay =10 cycles SEQ_CLK = 200 kHz AGC Settling = 10 x 5 s x 5 = 250 s Minimum AGC_Wait_Time must be at least 25 s.
RSSI Formula (Converting to dBm) Input_Power [dBm] = -120 dBm + (Readback_Code + Gain_Mode_Correction) x 0.5
where: Readback_Code is given by Bit RV7 to Bit RV1 in the readback register (see the Readback Format section). Gain_Mode_Correction is given by the values in Table 9.
IFWR
IFWR
IFWR
IFWR
CLK ADC RSSI
05876-018
R
LNA gain (LG2, LG1) and filter gain (FG2, FG1) are obtained from Register 9.
Table 9. Gain Mode Correction
LNA Gain (LG2, LG1) H (1, 0) H (1, 0) M (0, 1) L (0, 0) L (0, 0) Filter Gain (FG2, FG1) H (1, 0) M (0, 1) M (0, 1) M (0,1) L (0, 0) Gain Mode Correction TBD TBD TBD TBD TBD
Figure 20. RSSI Block Diagram
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD, the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD, the gain is increased. A delay (AGC_DELAY) is programmed to allow for settling of the loop. All of these parameters are set in Register 9. The user can program the two threshold values (defaults 30 and 70) and the delay value (default 10). The default AGC setup values should be adequate for most applications. The threshold values must be chosen to be more than 30 apart for the AGC to operate correctly.
An additional factor should be introduced to account for losses in the front-end-matching network/antenna.
Offset Correction Clock
In Register 3, the user should set the BB Offset Clock Divide Bits R3_DB[4:5] to give an offset clock between 1 MHz and 2 MHz: BBOS_CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE) where: BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
FSK DEMODULATORS ON THE ADF7021
There are four demodulators on the ADF7021:
* * * *
2FSK correlator/demodulator 2FSK linear demodulator 3FSK demodulator 4FSK demodulator
Select these using the Demod Scheme Bits, R4_DB[4:6].
AGC Information and Timing
AGC is selected by default and operates by selecting the appropriate LNA and filter gain settings for the measured RSSI level. It is possible to disable AGC by writing to Register 9 if the user wants to enter one of the modes listed in Table 8. The time for the AGC circuit to settle and therefore, the time it takes to measure the RSSI accurately, is typically 150 s. However, this depends on how many gain settings the AGC circuit has to cycle through. After each gain change, the AGC loop waits for a programmed time to allow transients to settle. This wait time can be altered to speed up the settling by adjusting the appropriate parameters.
FSK CORRELATOR/DEMODULATOR
The quadrature outputs of the IF filter are first limited and then fed to a pair of digital frequency correlators that perform bandpass filtering of the binary FSK frequencies at (IF + FDEV) and (IF - FDEV). Data is recovered by comparing the output levels from each of the two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of AWGN.
AGC _ Wait _ Time =
AGC _ Delay x SEQ _ CLK _ DIVIDE XTAL
Rev. PrI | Page 19 of 44
ADF7021
FREQUENCY CORRELATOR SLICER
Preliminary Technical Data
DATA SYNCHRONIZER POST DEMOD FILTER
IF RxDATA
Discriminator_BW = DEMOD_CLK x K/(400 x 103) where: DEMOD_CLK is as defined in the Register 3-- Transmit/Receive Clock Register Comments section. K = Round (100e3/Fdeviation) and Fdeviation is the 2FSK frequency deviation in Hz. To optimize the coefficients of the 2FSK correlator, Bits R4_DB7 and R4_DB[8:9] must be assigned. The value of these bits depends on whether K is odd or even. These bits are assigned according to Table 10 and Table 11.
Table 10. When K Is Even
K Even Even K/2 Even Odd R4_DB7 0 0 R4_DB[8:9] 00 10
I LIMITERS Q IF - FDEV
RxCLK
IF + FDEV
0 R4_DB(10:19) R4_DB(7) R4_DB(9) R4_DB(20:29) R3_DB(10:17)
05876-019
Figure 21. FSK Correlator/Demodulator Block Diagram
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user's data rate. If the bandwidth is set too narrow, performance is degraded due to intersymbol interference (ISI). If the bandwidth is set too wide, excess noise degrades the receiver's performance. Typically, the 3 dB bandwidth of this filter is set at approximately 0.75 times the user's data rate, using Bits R4_DB[20:29].
Table 11. When K Is Odd
K Odd Odd (K + 1)/2 Even Odd R4_DB7 1 1 R4_DB[8:9] 00 10
Bit Slicer
The received data is recovered by threshold detecting the output of the postdemodulator low-pass filter. In the correlator/demodulator, the binary output signal levels of the frequency discriminator are always centered on 0. Therefore, the slicer threshold level can be fixed at 0 and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery, which does not suffer from the classic baseline wander problems that exist in the more traditional FSK demodulators. Frequency errors are removed by an internal AFC loop that measures the average IF frequency at the limiter output and applies a frequency correction value to the fractional-N synthesizer. This loop should be activated when the frequency errors are greater than approximately 40% of the transmit frequency deviation.
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled by Bits R4_DB[20:29] and is given by
Post _ Demod _ BW _ Setting = 211 x x FCUTOFF DEMOD _ CLK
where: FCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter. This should typically be set to 0.75 times the data rate (DR). Some sample settings for the FSK correlator/demodulator are DEMOD_CLK = 11.0592 MHz DR = 9.6 kbps FDEV = 4.8 kHz therefore, FCUTOFF = 0.75 x 9.6 x 103 Hz Post_Demod_BW = 211 x x 7.2 x 103 Hz/(11.0592 x 106) Post_Demod_BW = Round(4.188) = 4 and K = Round(100 kHz)/4.8 kHz) = 21 Discriminator_BW = (11.0592 x 106 x 21)/(400 x 103) = 580.6 = 581 (rounded to nearest integer)
Table 12. Example Register Settings
Setting Name Post_Demod_BW Discriminator BW Dot Product Rx Data Invert Register Address R4_DB[20:29] R4_DB[10:19] R4_DB7 R4_DB[8:9] Value 0x04 0x245 1 10
Data Synchronizer
An oversampled digital PLL is used to resynchronize the received bit stream to a local clock. The oversampled clock rate of the PLL (CDR_CLK) must be set at 32 times the data rate. See the Register 3--Transmit/Receive Clock Register section for programming notes. The clock recovery PLL can accommodate frequency errors of up to 2%.
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB[4:6] should be set to 001. To achieve best performance, the bandwidth of the 2FSK correlator must be optimized for the specific deviation frequency that is used by the 2FSK transmitter. The discriminator BW is controlled in Register 4 by DB[10:19] and is defined as
Rev. PrI | Page 20 of 44
Preliminary Technical Data
LINEAR 2FSK DEMODULATOR
Figure 22 shows a block diagram of the linear 2FSK demodulator.
SLICER LEVEL I LIMITER Q FREQUENCY LINEAR DISCRIMINATOR
ADF7021
3FSK DEMODULATOR
The 3FSK demodulator uses a pair of digital frequency correlators followed by a Viterbi decoder and clock and data recovery to perform three-level FSK demodulation. To enable 3FSK demodulation, Bits R4_DB[4:6] must be set to 010. The settings for the 3FSK demodulator are set in Register 13. The post demod BW, discriminator BW, dot product, and Rx invert settings of Register 4 also need to be set appropriately as outlined in the FSK Correlator/Demodulator section.
AVERAGING FILTER
IF
RxDATA
ENVELOPE DETECTOR
R4_DB(20:29)
Figure 22. Block Diagram of Frequency Measurement System and Linear FSK Demodulator
This method of frequency demodulation is useful when the system protocol cannot support the overhead of the settling time of the internal feedback AFC loop. A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. The discriminator output is then filtered and averaged using a combined averaging filter and envelope detector. The demodulated 2FSK data is recovered by threshold detecting the output of the averaging filter, as shown in Figure 22. In this mode, the slicer output shown in Figure 22 is routed to the data synchronizer PLL for clock synchronization. To enable the linear FSK demodulator, set Bits R4_DB[4:6] to 000. The 3 dB bandwidth of the postdemodulation filter is set in the same way as the 2FSK correlator/demodulator, which is set in R4_DB[20:29] and is defined as
Post _ Demod _ BW _ Setting = 211 x x FCUTOFF DEMOD _ CLK
05876-020
FREQUENCY READBACK AND AFC LOOP
4FSK DEMODULATOR
The 4FSK demodulator uses a pair of digital frequency correlators and clock and data recovery to perform four-level FSK demodulation. To enable 4FSK demodulation, Bits R4_DB[4:6] must be set to 011. The post demod BW, discriminator BW, dot product, and Rx invert settings of Register 4 also need to be set appropriately as outlined in the FSK Correlator/Demodulator section.
AFC SECTION
The ADF7021 supports a real-time AFC loop that is used to remove frequency errors that can arise due to mismatches between the transmit and receive crystals. The AFC loop also uses the frequency discriminator block, as described in the Linear 2FSK Demodulator section and in Figure 22. The discriminator output is filtered and averaged to remove the FSK frequency modulation using a combined averaging filter and envelope detector. In receive mode, the output of the envelope detector provides an estimate of the average IF frequency. Two methods of AFC, external and internal, are supported on the ADF7021.
External AFC
Here, the user reads back the frequency information through the ADF7021 serial port and applies a frequency correction value to the fractional-N synthesizer N divider. The frequency information is obtained by reading the 16-bit signed AFC_readback, as described in the Readback Format section, and by applying the following formula: FREQ_RB [Hz] = (AFC_READBACK x DEMOD_CLK)/218 Note that while the AFC_READBACK value is a signed number, under normal operating conditions it is positive. In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 100 kHz.
where: FCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter. DEMOD_CLK is as defined in the Register 3-- Transmit/Receive Clock Register Comments section.
Rev. PrI | Page 21 of 44
ADF7021
Internal AFC
The ADF7021 supports a real-time, internal, automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer-N divider using an internal PI control loop. The internal AFC control loop parameters are controlled in Register 10. The internal AFC loop is activated by setting R10_DB4 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up in R10_DB[5:16] and should be calculated using AFC_Scaling_Coefficient = (500 x 224)/XTAL
Preliminary Technical Data
AUTOMATIC SYNC WORD RECOGNITION
The ADF7021 also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7021. In receive mode, this preprogrammed word is compared to the received bit stream, and when a valid match is identified, the external SWD pin is asserted by the ADF7021 on the next Rx clock pulse. This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The SWD signal can also be used to frame a received packet length by staying high for a preprogrammed number of bytes. The data packet length can be set in Bits R12_DB[8:15]. The SWD pin status can be configured by setting Bits R12_DB[6:7]. Bits R11_DB[4:5] are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync-bytedetection hardware. For systems using FEC, an error tolerance parameter can also be programmed that accepts a valid match when up to 3 bits of the word are incorrect. The error tolerance value is assigned in R11_DB[6:7].
Maximum AFC Range
The maximum AFC frequency range is 127.5 kHz. This is set by Bits R10_DB[24:31]. The maximum AFC pull-in range should be less than or equal to half the channel spacing to prevent the AFC pulling in a signal in the adjacent channel. If the maximum AFC pull-in range is larger than the IF filter bandwidth, the attenuation of the IF filter must be considered. When AFC errors have been removed using either the internal or external AFC, further improvement in the receiver's sensitivity can be obtained by reducing the IF filter bandwidth using Bits R4_DB[30:31].
Rev. PrI | Page 22 of 44
Preliminary Technical Data APPLICATIONS
LNA/PA MATCHING
The ADF7021 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption, only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7021 is equipped with an internal Rx/Tx switch that facilitates the use of a simple, combined passive PA/LNA matching network. Alternatively, an external Rx/Tx switch such as the ADG919 can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption.
ADF7021
input reflection coefficient and the maximum differential signal swing at the LNA input must be established. The use of appropriate CAD software is strongly recommended for this optimization. Depending on the antenna configuration, the user might need a harmonic filter at the PA output to satisfy the spurious emission requirement of the applicable government regulations. The harmonic filter can be implemented in various ways, such as a discrete LC pi or T-stage filter. Dielectric low-pass filter components, such as the LFL18924MTC1A052 (for operation in the 915 MHz and 868 MHz band) by Murata Manufacturing Co. Ltd., represent an attractive alternative to discrete designs. The immunity of the ADF7021 to strong out-of-band interference can be improved by adding a band-pass filter in the Rx path. Apart from discrete designs, SAW or dielectric filter components such as the SAFCH869MAM0T00B0S, SAFCH915MAL0N00B0S, DCFB2869MLEJAA-TT1, or DCFB3915MLDJAA-TT1, all by Murata Manufacturing Co. Ltd., are well suited for this purpose. Alternatively, the ADF7021 blocking performance can be improved by selecting the high linearity mode, as described in Table 8.
External Rx/Tx Switch
Figure 23 shows a configuration using an external Rx/Tx switch. This configuration allows an independent optimization of the matching and filter network in the transmit and receive path. Therefore, it is more flexible and less difficult to design than the configuration using the internal Rx/Tx switch. The PA is biased through Inductor L1, while C1 blocks dc current. Both elements, L1 and C1, also form the matching network that transforms the source impedance into the optimum PA load impedance, ZOPT_PA.
VBAT L1
Internal Rx/Tx Switch
Figure 24 shows the ADF7021 in a configuration where the internal Rx/Tx switch is used with a combined LNA/PA matching network. For most applications, the slight performance degradation of 1 dB to 2 dB caused by the internal Rx/Tx switch is acceptable, allowing the user to take advantage of the costsaving potential of this solution. The design of the combined matching network must compensate for the reactance presented by the networks in the Tx and the Rx paths, taking the state of the Rx/Tx switch into consideration.
VBAT
OPTIONAL LPF ANTENNA
C1
PA_OUT PA
ZOPT_PA ZIN_RFIN OPTIONAL CA BPF (SAW) LA RFIN LNA
RFINB
ADG919
Rx/Tx - SELECT CB
ADF7021
05876-021
ZIN_RFIN
C1
L1
PA_OUT PA
Figure 23. ADF7021 with External Rx/Tx Switch
CB
ADF7021
Due to the differential LNA input, the LNA matching network must be designed to provide both a single-ended to differential conversion, and a complex conjugate impedance match. The network with the lowest component count that can satisfy these requirements is the configuration shown in Figure 23, consisting of two capacitors and one inductor. A first-order implementation of the matching network can be obtained by understanding the arrangement as two L-type matching networks in a back-to-back configuration. Due to the asymmetry of the network with respect to ground, a compromise between the
Figure 24. ADF7021 with Internal Rx/Tx Switch
The procedure typically requires several iterations until an acceptable compromise has been reached. The successful implementation of a combined LNA/PA matching network for the ADF7021 is critically dependent upon the availability of an accurate electrical model for the PC board. In this context, the use of a suitable CAD package is strongly recommended. To avoid this effort, the reference design provided for the ADF7021 RF module can be used. Gerber files are available on request.
Rev. PrI | Page 23 of 44
05876-022
ZOPT_PA depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. Selecting an appropriate ZOPT_PA helps to minimize the Tx current consumption in the application. Application Note AN-764 contains a number of ZOPT_PA values for representative conditions. Under certain conditions however, it is recommended to obtain a suitable ZOPT_PA value by means of a load-pull measurement.
ANTENNA
OPTIONAL BPF OR LPF CA
ZOPT_PA ZIN_RFIN RFIN LA LNA
RFINB
ZIN_RFIN
ADF7021
As with the external Rx/Tx switch, an additional LPF or BPF could be required to suppress harmonics in the transmit spectrum or to improve the resilience of the receiver against out-of-band interferers.
Preliminary Technical Data
If longer run-length coding must be supported, the ADF7021 has several other features that can be activated. These involve a range of programmable options that allow the envelope detector output to be frozen after preamble acquisition.
TRANSMIT PROTOCOL AND CODING CONSIDERATIONS
PREAMBLE DATA FIELD CRC
05876-023
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
Table 13 lists the minimum number of writes needed to set up the ADF7021 in either Tx or Rx mode after CE is brought high. Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling AFC. When going from Tx to Rx or vice versa, the user needs to write only to Register 1 to alter the LO by 100 kHz and to toggle the Tx/Rx bit.
Table 13. Minimum Register Writes Required for Tx/Rx Setup
Mode Tx Rx Tx <-> Rx Registers Reg 0 Reg 1 Reg 0 Reg 1 Reg 0 Reg 2 Reg 3 Reg 3 Reg 4
SYNC WORD
ID FIELD
Figure 25. Typical Format of a Transmit Protocol
A dc-free preamble pattern is recommended for FSK demodulation. The recommended preamble pattern is a dc-free pattern such as a 10101010 ... pattern. Preamble patterns with longer run-length constraints such as 11001100... can also be used. However, this results in a longer synchronization time of the received bit stream in the receiver. Manchester coding can be used for the entire transmit protocol. However, the remaining fields that follow the preamble header do not have to use dc-free coding. For these fields, the ADF7021 can accommodate coding schemes with a run length of up to 6 bits without any performance degradation.
ADF7021 I DD
Reg 5
Figure 26 and Figure 27 show the recommended programming sequence and associated timing for power-up from standby mode.
19mA TO 22mA
12mA
XTAL
t0
3.65mA 2.0mA
AFC
t13
REG. READY
tON
tOFF
Figure 26. Rx Programming Sequence and Timing Diagram
Rev. PrI | Page 24 of 44
05876-024
t1
t2
WR1
t3
VCO
t4
WR3 WR6 WR5
t5
t6
t7
t8
WR0 WR4
t9
t10
AGC/ RSSI
CDR
t11
t12
RxDATA
t14
TIME
Preliminary Technical Data
ADF7021 I DD
ADF7021
11mA TO 30mA
14mA XTAL
t0
3.65mA
2.0mA
REG. READY
t1
t2
WR1
t3
VCO
t4
WR3 WR0 WR4
t5
t6
t7
TRANSMIT DATA
t15
TIME
05876-025
tON
tOFF
Figure 27. Tx Programming Sequence and Timing Diagram
Table 14. Power-Up Sequence Description
Parameter T0 T1 T2 Value 2 ms typ 10 s 1ms typ Description/Notes Crystal starts power-up after CE is brought high. This typically depends on the specified crystal type and load capacitance. Time for regulator to power up. The serial interface can be written to after this time. Variable delay that depends on XTAL settling and VCO settling. Should be set so that VCO and XTAL finish settling at the same time, thus minimizing current consumption. Time to write to a single register. Maximum SPI_CLK is 25 MHz. The VCO can power up in parallel with the crystal. This depends on the CVCO capacitance value used. A value of 22 nF is recommended as a trade-off between phase noise performance and power-up time. IF filter coarse and fine calibration times. A coarse calibration typically takes 200 s, while a fine calibration typically takes 3 ms (see the settings in the Register 7--Readback Setup Register section). This depends on the number of gain changes the AGC loop needs to cycle through and AGC settings programmed. This is described in more detail in the AGC Information and Timing section. This is the time for the clock and data recovery circuit to settle. This typically requires 5-bit transitions to acquire sync and is usually covered by the preamble. This is the time for the automatic frequency control circuit to settle. This typically requires 16-bit transitions to acquire lock and is usually covered by an appropriate length preamble. Number of bits in payload by the bit period. Signal to Monitor CLKOUT MUXOUT
T3, T5,T6, T7, T9, T10 T4
32 x 1/SPI_CLK 1 ms
CVCO pin
T8
3.2 ms
T11
150 s
Analog RSSI on TEST_A pin (available by writing 0x0B00 000F)
T12 T13
5 x Bit_Period 20 x Bit_Period
T14, T15
Packet length
Rev. PrI | Page 25 of 44
ADF7021
INTERFACING TO MICROCONTROLLER/DSP
Low level device drivers are available for interfacing to the ADF7021, such as the ADuC84x microcontroller parts, or the Blackfin(R) ADSP-BF53x DSPs. Use the hardware connections shown in Figure 28 and Figure 29.
ADuC84x MISO MOSI SCLOCK SS P3.7 P3.2/INT0 P2.4 GPIO P2.5 P2.6 P2.7
Preliminary Technical Data
ADF7021
TxRxDATA RxCLK CE INT/LOCK SREAD SLE SDATA SCLK
05876-026 05876-028 05876-027
UART Mode
If a data synchronization clock is not required, the DATA_CLK| TxDATA pin can be configured to input transmit data in transmit mode. In receive mode, the receive data is available on the DATA_I/O|RxDATA pin. This allows a UART to be easily interfaced to the part, with dedicated pins for transmitted and received data, as shown in Figure 30. To enable this UART interface mode, set Bit R0_DB28 high.
Figure 28. ADuC84x to ADF7021 Connection Diagram
ADSP-BF533 SCK MOSI MISO PF5 RSCLK1 DT1PRI DR1PRI RFS1 PF6 VCC GND
ADF7021
SCLK SDATA SREAD SLE RxCLK/DATA TxRxDATA RxCLK/DATA CE VCC GND
Figure 29. ADSP-BF533 to ADF7021 Connection Diagram
UART TxDATA
ADF7021
DATA_CLK | TxDATA
RxDATA
DATA I/O | RxDATA
Figure 30. UART to ADF7021 Connection Diagram
Rev. PrI | Page 26 of 44
Preliminary Technical Data SERIAL INTERFACE
The serial interface allows the user to program the 16, 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a level shifter, 32-bit shift register, and 16 latches. Signals should be CMOS-compatible. The serial interface is powered by the regulator, and, therefore, is inactive when CE is low. Data is clocked into the register, MSB first, on the rising edge of each clock (SCLK). Data is transferred to one of 16 latches on the rising edge of SLE. The destination latch is determined by the value of the four control bits (C4 to C1). These are the bottom 4 LSBs, DB3 to DB0, as shown in Figure 2. Data can also be read back on the SREAD pin.
ADF7021
RSSI Readback
The RSSI readback operation yields valid results in Rx mode with ASK or FSK signals. The format of the readback word is shown in Figure 31. It is comprised of the RSSI level information (Bit RV1 to Bit RV7), the current filter gain (FG1, FG2), and the current LNA gain (LG1, LG2) setting. The filter and LNA gain are coded in accordance with the definitions in Register 9. With the reception of ASK modulated signals, averaging of the measured RSSI values improves accuracy. The input power can be calculated from the RSSI readback value as outlined in the RSSI/AGC.
READBACK FORMAT
The readback operation is initiated by writing a valid control word to the readback register and setting the readback-enable bit (R7_DB8 = 1). The readback can begin after the control word has been latched with the SLE signal. SLE must be kept high while the data is being read out. Each active edge at the SCLK pin clocks the readback word out successively at the SREAD pin, as shown in Figure 31, starting with the MSB first. The data appearing at the first clock cycle following the latch operation must be ignored.
Battery Voltage ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback information is contained in Bit RV1 to Bit RV7. This also applies for the readback of the voltage at the ADCIN pin and the temperature sensor. From the readback information, the battery or ADCIN voltage can be determined using VBATTERY = (Battery_Voltage_Readback)/21.1 VADCIN = (ADCIN_Voltage_Readback)/42.1
Silicon Revision Readback
The silicon revision readback word is valid without setting any other registers, especially directly after power-up. The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with three quartets extending from Bit RV5 to Bit RV16. The revision code (RV) is coded with one quartet extending from Bit RV1 to Bit RV4. The product code for the ADF7021 should read back as PC = 0x210. The current revision code should read as RC = 0x2.
AFC Readback
The AFC readback is valid only during the reception of FSK signals with either the linear or correlator demodulator active. The AFC readback value is formatted as a signed 16-bit integer comprised of Bit RV1 to Bit RV16, and is scaled according to the following formula: FREQ_RB [Hz] = (AFC_READBACK x DEMOD_CLK)/218 In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 100 kHz. Note that for the AFC readback to yield a valid result, the down converted input signal must not fall outside the bandwidth of the analog IF filter. At low-input signal levels, the variation in the readback value can be improved by averaging.
Filter Calibration Readback
The filter calibration readback word is contained in Bit RV1 to Bit RV8, and is for diagnostic purposes only. Using the automatic filter calibration function (accessible through Register 5 and Register 6) is recommended. Before filter calibration is initiated, decimal 32 should be read back.
READBACK MODE DB15 AFC READBACK RSSI READBACK BATTERY VOLTAGE/ADCIN/ TEMP. SENSOR READBACK SILICON REVISION FILTER CAL READBACK RV16 X DB14 RV15 X DB13 RV14 X DB12 RV13 X DB11 RV12 X DB10 RV11 LG2
READBACK VALUE DB9 RV10 LG1 DB8 RV9 FG2 DB7 RV8 FG1 DB6 RV7 RV7 DB5 RV6 RV6 DB4 RV5 RV5 DB3 RV4 RV4 DB2 RV3 RV3 DB1 RV2 RV2 DB0 RV1 RV1
X RV16 0
X RV15 0
X RV14 0
X RV13 0
X RV12 0
X RV11 0
X RV10 0
X RV9 0
X RV8 RV8
RV7 RV7 RV7
RV6 RV6 RV6
RV5 RV5 RV5
RV4 RV4 RV4
RV3 RV3 RV3
RV2 RV2 RV2
RV1
05876-029
RV1 RV1
Figure 31. Readback Value Table
Rev. PrI | Page 27 of 44
ADF7021
REGISTER 0--N REGISTER
UART MODE Tx/Rx
MUXOUT 8-BIT INTEGER-N
Preliminary Technical Data
15-BIT FRACTIONAL-N
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (0)
C4 (0)
C3 (0)
TR1 0 1 U1 0 1 M3 0 0 0 0 1 1 1 1 M2 0 0 1 1 0 0 1 1 M1 0 1 0 1 0 1 0 1
TRANSMIT/ RECEIVE TRANSMIT RECEIVE
M15 0 0 0 . . . 1 1 1 1
M14 0 0 0 . . . 1 1 1 1
M13 0 0 0 . . . 1 1 1 1
... ... ... ... ... ... ... ... ... ... ...
M3 0 0 0 . . . 1 1 1 1
M2 0 0 1 . . . 0 0 1 1
M1 0 1 0 . . . 0 1 0 1
FRACTIONAL DIVIDE RATIO 0 1 2 . . . 32764 32765 32766 32767
UART MODE DISABLED ENABLED MUXOUT REGULATOR READY (DEFAULT) END OF CAL DIGITAL LOCK DETECT RSSI READY Tx_Rx LOGIC ZERO THREE STATE LOGIC ONE
N8 0 0 . . . 1 1 1
N7 0 0 . . . 1 1 1
N6 0 1 . . . 1 1 1
N5 1 0 . . . 1 1 1
N4 1 0 . . . 1 1 1
N3 1 0 . . . 1 1 1
N2 1 0 . . . 0 1 1
N1 1 0 . . . 1 0 1
N COUNTER DIVIDE RATIO 31 32 . . . 253 254 255
C1 (0)
05876-030
M15
M14
M13
M12
M10
TR1
M11
M3
M2
M1
M9
M8
M7
M6
M5
M4
M3
M2
Figure 32.
Register 0--N Register Comments
*
RF Output Frequency
Fractional _ N Direct output: RFOUT = PFD x Integer _ N + 2 15 Fractional _ N Divide-by-2 selected: RFOUT = PFD x 0.5 x Integer _ N + 2 15
* *
In UART mode, the DATA CLK | TxDATA pin is used to input the Tx data. The Rx Data is available on the DATA I/O | RxDATA pin. MUXOUT END OF CAL (Active High): Indicates when a fine IF filter calibration has finished. DIGITAL LOCK DETECT (Active High): Indicates when the PLL has locked. RSSI READY (Active High): Indicates RSSI signal has settled and RSSI readback can be performed. Tx_Rx: Gives the status of Bit DB27 in this register. Can be used to control an external Tx/Rx switch.
Rev. PrI | Page 28 of 44
M1
U1
N8
N7
N6
N5
N4
N3
N2
N1
DB0
Preliminary Technical Data
REGISTER 1--VCO/OSCILLATOR REGISTER
VCO INDUCTOR CP CURRENT XOSC ENABLE XTAL DOUBLER VCO ENABLE
ADF7021
VCO ADJUST
VCO /2
VCO BIAS
XTAL BIAS
CLOCKOUT DIVIDE
R COUNTER
ADDRESS BITS
DB24
DB23
DB22
DB21
DB20
DB19
VDV1 DB18
DB17
DB16
DB15
DB14
DB13
DB12
VCL1 DB25
DB10
DB11
DB3
DB2
DB1 C2 (0)
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0)
C3 (0)
VA2 0 0 1 1
VA1 0 1 0 1
VCO CENTER FREQ ADJUST NOMINAL VCO ADJUST UP 1 VCO ADJUST UP 2 VCO ADJUST UP 3
VB1 VCO /2 0 1 /2 OFF /2 ON
R3 0 0 . . . 1
R2 0 1 . . . 1
R1 1 0 . . . 1
RF R COUNTER DIVIDE RATIO 1 2 . . . 7 CLKOUT DIVIDE RATIO OFF 2 4 . . . 30
VB4 0 0 . 1
VB3 0 0 . 1
VB2 0 1 . 1
VB1 1 0 . 1
VCO BIAS CURRENT 0.25mA 0.5mA 4mA LOOP CONDITION VCO OFF VCO ON D1 0 1 CP1 RSET 0 1 0 1 ICP (mA) 3.6k 0.3 0.9 1.5 2.1
VE1 VCL1 0 1 VCO INDUCTOR INTERNAL EXTERNAL 0 1
CL4 0 0 0 . . . 1 XTAL DOUBLER DISABLE ENABLED
CL3 0 0 0 . . . 1
CL2 0 0 1 . . . 1
CL1 0 1 0 . . . 1
CP2 0 0 1 1
X1 XTAL OSC 0 OFF 1 ON XB2 XB1 0 0 1 1 0 1 0 1 XTAL BIAS 20A 25A 30A 35A
C1 (1)
05876-031
VB4
VB3
VB2
VB1
XB2
XB1
CP2
CP1
CL4
CL3
CL2
VA2
VA1
CL1
VE1
D1
R3
R2
Figure 33.
Register 1--VCO/Oscillator Register N Comments
* R_DIVIDE and XTAL DOUBLER If XTAL DOUBLER = 0, PFD =
XTAL R _ DIVIDE XTAL x 2 R _ DIVIDE
If XTAL DOUBLER =1, PFD = * * * *
CLOCKOUT is a divided-down version of the XTAL and is available on Pin 36 (CLKOUT). XOSC_ENABLE should be set high when using an external crystal. If using an external oscillator (such as TCXO, OCXO) with CMOS-level outputs into Pin OSC2, the XOSC enable should be set low. The VCO_ADJUST bits adjust the center of the VCO operating band. Each bit typically adjusts the VCO band up by 1% of the RF operating frequency (0.5% if divide-by-2 is enabled). Setting VCO_INDUCTOR to external allows the use of an external VCO tank inductor, which gives RF operating frequencies of 80 Hz to 650 MHz. If the internal inductor is being used for operation, this bit should be set low.
Rev. PrI | Page 29 of 44
R1
X1
DB0
ADF7021
REGISTER 2--TRANSMIT MODULATION REGISTER
NARROW BAND RC
Preliminary Technical Data
PA ENABLE
TxDATA INVERT
Tx FREQUENCY DEVIATION
POWER AMPLIFIER
PA BIAS
PA RAMP
MODULATION SCHEME
ADDRESS BITS
NRC1 DB30
DB29
DB28
TFD9 DB27
TFD8 DB26
TFD7 DB25
TFD6 DB24
TFD5 DB23
TFD4 DB22
TFD3 DB21
TFD2 DB20
TFD1 DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (1)
C4 (0)
C3 (0)
PA2 0 0 1 1 DI2 0 0 1 1 DI1 0 1 0 1 TxDATA INVERT NORMAL INVERT CLK INVERT DATA INV CLK AND DATA S3 0 0 0 0 1 1 1 1
PA1 0 1 0 1
PA BIAS 5A 7A 9A 11A
PE1 0 1
POWER AMPLIFIER OFF ON
S2 0 0 1 1 0 0 1 1
S1 0 1 0 1 0 1 0 1
PA RAMP RATE NO RAMP 256 CODES/BIT 128 CODES/BIT 64 CODES/BIT 32 CODES/BIT 16 CODES/BIT 8 CODES/BIT 4 CODES/BIT S3 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S1 0 1 0 1 0 1 0 1 MODULATION SCHEME 2FSK GAUSSIAN 2FSK 3FSK 4FSK OVERSAMPLED 2FSK RAISED CONSINE FILTER 2FSK RAISED CONSINE FILTER 3FSK RAISED CONSINE FILTER 4FSK
FOR FSK MODE, D2 ... D3 D9
D1 0 1 0 1 . 1 PLL MODE 1 x fSTEP 2 x fSTEP 3 x fSTEP . 511 x fSTEP
0 0 0 0 . 1
... ... ... ... ... ...
0 0 0 0 . 1
0 0 1 1 . 1
NARROWBAND NRC1 RC 0 1 DEFAULT EXTRA FILTERING
POWER AMPLIFIER OUTPUT HIGH LEVEL . . P6 P1 P2
Figure 34.
Register 2--Transmit Modulation Register Comments
* 2FSK/3FSK/4FSK frequency deviation Direct output: Frequency Deviation[Hz] = Divide-by-2 enabled: Frequency Deviation[Hz] = 0.5 x TX_FREQUENCY_DEVIATION x PFD 2 16 TX_FREQUENCY_DEVIATION x PFD 2 16
where: TX_FREQUENCY_DEVIATION is set by R2_DB[19:27] and PFD is the PFD frequency. * * * * In the case of 4FSK, there are tones at 3 times the frequency deviation and at 1 times the deviation. Oversampled 2FSK is sampled at 32 times the programmed data rate. The PA ramps at the programmed rate (R2_DB[8:10]) until it reaches its programmed level (R2_DB[13:18]). If the PA is enabled/disabled by the PA_Enable Bit (R2_DB7), it ramps up and down. If it is enabled/disabled by the Tx_Rx bit (R0_DB27), it ramps up and turns hard off.
Rev. PrI | Page 30 of 44
05876-032
0 0 0 0 . . 1
. . . . . . 1
. . . . . . .
X 0 0 1 . . 1
X 0 1 0 . . 1
PA OFF -16.0dBm -16 + 0.45dBm -16 + 0.90dBm . . 13dBm
C1 (0)
PR3
PR2
PR1
PA2
PA1
PE1
DI2
DI1
P6
P5
P4
P3
P2
P1
S3
S2
S1
DB0
Preliminary Technical Data
REGISTER 3--TRANSMIT/RECEIVE CLOCK REGISTER
DEMOD CLOCK DIVIDE BB OFFSET CLOCK DIVIDE
ADF7021
AGC CLOCK DIVIDE
SEQUENCER CLOCK DIVIDE
CDR CLOCK DIVIDE
ADDRESS BITS
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (1)
C4 (0)
C3 (0)
SK8 0 0 . 1 1 GD6 0 0 ... 1 GD5 0 0 ... 1 GD4 0 0 ... 1 GD3 0 0 ... 1 GD2 0 0 ... 1 GD1 0 1 ... 1
SK7 0 0 . 1 1
... ... ... ... ... ...
SK3 0 0 . 1 1
SK2 0 1 . 1 1
SK1 1 0 . 0 1
SEQ_CLK_DIVIDE 1 2 . 254 255 0 0 ... 1
BK2 0 0 1 1 OK4 OK3 OK2 OK1
BK1 0 1 0 1
BBOS_CLK_DIVIDE 4 8 16 32
DEMOD_CLK_DIVIDE INVALID 1 ... 15
AGC_CLK_DIVIDE INVALID 1 ... 127
0 0 ... 1
0 0 ... 1
0 1 ... 1
FS8 0 0 . 1 1
FS7 0 0 . 1 1
... ... ... ... ... ...
FS3 0 0 . 1 1
FS2 0 1 . 1 1
FS1 1 0 . 0 1
CDR_CLK_DIVIDE 1 2 . 254 255
C1 (1)
05876-033
OK4
OK3
OK2
GD6
GD5
GD4
GD3
GD2
GD1
OK1
BK2
Figure 35.
Register 3--Transmit/Receive Clock Register Comments
* Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where: XTAL BBOS _ CLK = BBOS _ CLK _ DIVIDE Set the demodulator clock (DEMOD_CLK) such that 2 MHz DEMOD_CLK 15 MHz, where:
DEMOD _ CLK = * XTAL DEMOD _ CLK _ DIVIDE
*
Data/clock recovery frequency (CDR _CLK) needs to be within 2% of (32 x data rate). The user should choose CDR_CLK frequency to be as high as possible without breaking this 2% constraint or breaking the DEMOD_CLK condition. This 2% constraint can also affect the choice of XTAL frequency, depending on the desired data rate.
CDR _ CLK = DEMOD _ CLK CDR _ CLOCK _ DIVIDE
The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be as close to 100 kHz as possible. XTAL SEQ _ CLK = SEQUENCER _ CLOCK _ DIVIDE * The time allowed for each AGC step to settle is determined by the AGC update rate. It should be set close to 20 kHz.
AGC Update Rate [Hz] = SEQ _ CLK AGC _ DIVIDE
Rev. PrI | Page 31 of 44
BK1
SK8
SK7
SK6
SK5
SK4
SK3
SK2
SK1
FS8
FS7
FS6
FS5
FS4
FS3
FS2
FS1
DB0
ADF7021
REGISTER 4--DEMODULATOR SETUP REGISTER
Preliminary Technical Data
DOT PRODUCT
IF B/W
POST DEMODULATOR BW
DISCRIMINATOR BW
Rx INVERT
DEMOD SCHEME
ADDRESS BITS
DB31
DB30
DW10 DB29
DW9 DB28
DW8 DB27
DW7 DB26
DW6 DB25
DW5 DB24
DW4 DB23
DW3 DB22
DW2 DB21
DW1 DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (0)
C4 (0)
C3 (1)
IF FILTER IFB2 IFB1 B/W 0 0 12kHz 0 1 18kHz 1 0 25kHz 1 1 INVALID
DP1 0 1
PRODUCT CROSS PRODUCT DOT PRODUCT
RI2 RI1 0 0 1 1 0 1 0 1
INVERT NORMAL INVERT CLK INVERT DATA INVERT CLK/DATA
DS3 DS2 DS1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
DEMODULATOR SCHEME 2FSK LINEAR DEMODULATOR 2FSK CORRELATOR/DEMODULATOR 3FSK DEMODULATOR 4FSK DEMODULATOR RESERVED RESERVED RESERVED RESERVED
C1 (0)
TD10
IFB1
DP1
DS3
DS2
IFB2
TD9
TD8
TD7
TD6
TD5
TD4
TD3
TD2
TD1
DS1
RI2
RI1
DB0
Figure 36.
Register 4--Demodulator Setup Register Comments
* Discriminator_BW =
DEMOD _ CLK x K 400 x 10 3
where: K= 100 x 10 3 Frequency Deviation[Hz]
Maximum value = 660. * RX_INVERT(R4_DB[8:9]) and DOT_PRODUCT (R4_DB7) need to be set as outlined below in order to optimize the correlator demodulator. K is calculated using the previous formula and then rounded to the nearest integer.
K/2 Even Odd (K + 1)/2 Even Odd Dot Product (R4_DB7) 0 0 Dot Product (R4_DB7) 1 1 Rx Invert (R4_DB[8:9]) 00 10 Rx Invert (R4_DB[8:9]) 00 10
K Even Even K Odd Odd
*
Post_Demod_BW =
2 11 x x FCUTOFF DEMOD _ CLK
where the cutoff frequency (FCUTOFF) of the postdemodulator filter should typically be 0.75 times the data rate.
Rev. PrI | Page 32 of 44
05876-034
Preliminary Technical Data
REGISTER 5--IF FILTER SETUP REGISTER
IR PHASE ADJUST DIRECTION IF CAL COARSE IR GAIN ADJUST UP/DN IR GAIN ADJUST I/Q
ADF7021
IR GAIN ADJUST MAG
IR PHASE ADJUST MAG
IF FILTER ADJUST
IF FILTER DIVIDER
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
IFA6 DB19
IFA5 DB18
IFA4 DB17
IFA3 DB16
IFA2 DB15
IFA1 DB14
IFD9 DB13
IFD8 DB12
IFD6 DB10
IFD7 DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (0)
C4 (0)
C3 (1)
CC1 0 1 PM3 0 0 0 . 1 PM2 0 0 0 . 1 IR PHASE PM1 PM1 ADJUST 0 0 1 . 1 0 1 0 . 1 0 1 2 ... 31 IFD9 . 0 0 . . . . 1 . . . . . . .
CAL NO CAL DO CAL
FILTER CLOCK IFD6 IFD5 IFD4 IFD3 IFD2 IFD1 DIVIDE RATIO 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 1 . . . . 1 1 0 . . . . 1 1 2 . . . . 511
PD1 0 1
IR PHASE ADJUST I/Q ADJUST I CH ADJUST Q CH IR GAIN GM2 GM1 ADJUST 0 0 1 . 1 0 1 0 . 1 0 1 2 ... 31 IFA6 0 0 0 . 0 1 1 1 1 1 ... ... ... ... ... ... ... ... ... ... ... IFA2 0 0 1 . 1 0 0 1 . 1
GM5 GM4 0 0 0 . 1 0 0 0 . 1
GM3 0 0 0 . 1
IF FILTER IFA1 ADJUST 0 1 0 . 1 0 1 0 . 1 0 x 300Hz -1 x 300Hz -2 x 300Hz ... -31 x 300Hz 0 x 300Hz 1 x 300Hz 2 x 300Hz ... 31 x 300Hz
GQ1 IR GAIN ADJUST I/Q 0 1 GA1 0 1 ADJUST I CH ADJUST Q CH IR GAIN ADJUST UP/DN GAIN ATTENUATE
C1 (1)
05876-035
IFD5
IFD4
IFD3
IFD2
GM5
GM4
GM3
GM2
GM1
GQ1
GA1
PM4
PM3
PM2
IFD1
PD1
PM1
Figure 37.
Register 5--IF Filter Setup Register Comments
* * A coarse IF filter calibration is performed when the Coarse Cal Bit (R5_DB4) is set. If the Fine Cal Bit (R6_DB4) in is set, a fine IF filter calibration is performed after the coarse calibration. Set IF_Filter_DIVIDE such that
XTAL = 50 kHz IF _ FILTER _ DIVIDE
*
IF_FILTER_ADJUST allows the IF filter response to be manually adjusted in 300 Hz steps.
Rev. PrI | Page 33 of 44
CC1
DB0
ADF7021
REGISTER 6--IF FINE CAL SETUP REGISTER
Preliminary Technical Data
IF FINE CAL
IF CAL DWELL TIME
IF CAL UPPER TONE DIVIDER
IF CAL LOWER TONE DIVIDER
ADDRESS BITS
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (1)
C4 (0)
C3 (1)
UT8 0 0 0 . . 1
... ... ... ... ... ... ...
UT3 0 0 0 . . 1
UT2 0 1 1 . . 1
UT1 1 0 1 . . 1
IF CAL UPPER TONE DIVIDE 1 2 3 . . 255
FC1 0 1
IF FINE CAL DISABLED ENABLED
LT8 IF CAL CD3 CD2 CD1 DWELL TIME 0 0 0 . . 1 0 1 1 . . 1 1 0 1 . . 1 1 2 3 . . 127 0 0 0 . . 1
... ... ... ... ... ... ...
LT3 0 0 0 . . 1
LT2 0 1 1 . . 1
LT1 1 0 1 . . 1
IF CAL LOWER TONE DIVIDE 1 2 3 . . 255
05876-036
CD7 0 0 0 . . 1
... ... ... ... ... ... ...
Figure 38.
Register 6--IF Fine Cal Setup Register Comments
* * A fine IF filter calibration is set by enabling the IF_FINE_CAL Bit (DB4). A fine calibration is then carried out only when Register 5 is written to and Bit R5_DB4 is set. The IF upper and lower tones used during fine filter calibration should be set as follows: XTAL = 160 kHz IF _ CAL _ LOWER _ TONE _ DIVIDE XTAL = 220 kHz IF _ CAL _ UPPER _ TONE _ DIVIDE * The IF tone calibration time is the amount of time that is spent at an IF calibration tone. It is dependent upon the sequencer clock. It is recommended to have the IF_CAL_DWELL_TIME be at least 300 s. IF Tone Calibration Time = IF _ CAL _ DWELL SEQ _ CLK
The total time for a fine IF filter calibration is = IF Tone Calibration Time x 10.
Rev. PrI | Page 34 of 44
C1 (0)
CD7
CD6
CD5
CD4
CD3
CD2
CD1
FC1
UT8
UT7
UT6
UT5
UT4
UT3
UT2
UT1
LT8
LT7
LT6
LT5
LT4
LT3
LT2
LT1
DB0
Preliminary Technical Data
REGISTER 7--READBACK SETUP REGISTER
READBACK SELECT DB8 RB3 DB7 RB2 DB6 RB1 ADC MODE DB5 AD2 DB4 AD1 DB3 C4 (0) CONTROL BITS DB2 C3 (1) DB1 C2 (1) DB0 C1 (1)
ADF7021
RB3 READBACK 0 1 DISABLED ENABLED RB2 RB1 READBACK MODE 0 0 1 1 0 1 0 1 AFC WORD ADC OUTPUT FILTER CAL SILICON REV
AD2 AD1 ADC MODE 0 0 1 1 0 1 0 1 MEASURE RSSI BATTERY VOLTAGE TEMP SENSOR TO EXTERNAL PIN
Figure 39.
Register 7--Readback Setup Register Comments
* Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or the voltage at the external pin in Rx mode, users need to disable AGC function in Register 9. To read back these parameters in Tx mode, first power up the ADC using Register 8, as this is off by default in Tx mode to save power. This is the recommended method of using the battery readback function, as most configurations typically require AGC. AFC readback: FREQ_RB [Hz] = (AFC_READBACK x DEMOD_CLK)/218 * * * VBATTERY = Battery_Voltage_Readback/21.1 VADCIN = ADCIN_Voltage_Readback/42.1 See the Readback Format section for more information.
*
Rev. PrI | Page 35 of 44
05876-037
ADF7021
REGISTER 8--POWER DOWN TEST REGISTER
Tx/Rx SWITCH ENABLE PA ENABLE Rx MODE LNA/MIXER ENABLE RESERVED COUNTER RESET LOG AMP ENABLE DEMOD ENABLE ADC ENABLE FILTER ENABLE
Preliminary Technical Data
SYNTH ENABLE
Rx RESET
CONTROL BITS
DB15 CR1
DB14
DB13
DB12 PD7
DB11 SW1
DB10 LE1
DB9 PD6
DB8 PD5
DB7 PD4
DB6 PD3
DB5
DB4 PD1
DB3
DB2
DB1
DB0
C4 (1) C3 (0) C2 (0) C1 (0)
CR1 COUNTER RESET 0 1 NORMAL RESET CDR RESET DEMOD RESET PD3 PD7 0 1 PA (Rx MODE) PA OFF PA ON PD4 SW1 Tx/Rx SWITCH 0 1 LE1 0 1 DEFAULT (ON) OFF PD5 LOG AMP ENABLE LOG AMP OFF LOG AMP ON PD6 0 1 DEMOD ENABLE DEMOD OFF DEMOD ON 0 1 0 1 ADC ENABLE ADC OFF ADC ON 0 1
PD1 0 1
SYNTH STATUS SYNTH OFF SYNTH ON
LNA/MIXER ENABLE LNA/MIXER OFF LNA/MIXER ON
FILTER ENABLE FILTER OFF FILTER ON
Figure 40.
Register 8--Power Down Test Register Comments
* * It is not necessary to write to this register under normal operating conditions. For a combined LNA/PA matching network, Bit R8_DB11 should always be set to 0, which enables the internal Tx_Rx switch. This is the power-up default condition.
Rev. PrI | Page 36 of 44
05876-038
Preliminary Technical Data
REGISTER 9--AGC REGISTER
LNA MODE MIXER LINEARITY LNA CURRENT FILTER CURRENT FILTER GAIN LNA GAIN AGC MODE AGC HIGH THRESHOLD AGC LOW THRESHOLD
ADF7021
ADDRESS BITS
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (0)
C4 (1)
C3 (0)
ML1 MIXER LINEARITY 0 1 LI2 0 DEFAULT HIGH LI1 0 LNA BIAS 800A (DEFAULT) 0 1 2 3
AGC MODE AUTO AGC MANUAL AGC FREEZE AGC RESERVED
AGC LOW GL7 GL6 GL5 GL4 GL3 GL2 GL1 THRESHOLD 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 1 . . . 1 1 1 0 1 1 0 . . . 0 1 1 1 0 1 0 . . . 1 0 1 1 2 3 4 . . . 61 62 63
LG1 LNA MODE 0 1 DEFAULT REDUCED GAIN FI1 0 1 FILTER CURRENT LOW HIGH FG2 FG1 0 0 1 1 0 1 0 1 FILTER GAIN 8 24 72 INVALID LG2 LG1 LNA GAIN
AGC HIGH GH7 GH6 GH5 GH4 GH3 GH2 GH1 THRESHOLD 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . 0 0 1 0 0 0 0 . . . 1 1 0 0 0 0 1 . . . 1 1 0 0 1 1 0 . . . 1 1 0 1 0 1 0 . . . 0 1 0 1 2 3 4 . . . 78 79 80
Figure 41.
Register 9--AGC Register Comments
* * * Default AGC_LOW_THRESHOLD = 30, default AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC section for details. AGC high and low settings must be more than 30 apart to ensure correct operation. LNA gain of 30 is available only if LNA mode, R9_DB25, is set to zero.
Rev. PrI | Page 37 of 44
05876-039
0 0 1 1
0 1 0 1
3 10 30 INVALID
C1 (1)
GM2
GM1
GH7
GH6
GH5
GH4
GH3
GH2
GH1
ML1
GL7
GL6
GL5
GL4
GL3
GL2
GL1
LG1
FG2
FG1
LG2
LG1
LI2
LI1
FI1
DB0
ADF7021
REGISTER 10--AFC REGISTER
Preliminary Technical Data
AFC EN
MAX AFC RANGE
KP
KI
AFC SCALING FACTOR
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (1)
C4 (1)
C3 (0)
KP3 KP2 0 0 . 1 0 0 . 1
KP1 KP 0 1 . 1 2^0 2^1 ... 2^7
KI4 0 0 . 1
KI3 0 0 . 1
KI2 0 0 . 1
KI1 0 1 . 1
KI 2^0 2^1 ... 2^15
AE1 0 1
AFC ENABLE OFF AFC ON
MA8 0 0 0 0 . . . 1 1 1
... ... ... ... ... ... ... ... ... ... ...
MAX AFC MA3 MA2 MA1 RANGE 0 0 0 1 . . . 1 1 1 0 1 1 0 . . . 0 1 1 1 0 1 0 . . . 1 0 1 1 2 3 4 . . . 253 254 255
M12 0 0 0 0 . . . 1 1 1
... ... ... ... ... ... ... ... ... ... ...
M3 0 0 0 1 . . . 1 1 1
M2 0 1 1 0 . . . 0 1 1
M1 1 0 1 0 . . . 1 0 1
AFC SCALING FACTOR 1 2 3 4 . . . 4093 4094 4095
C1 (0)
05876-040
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
M12
M10
KP3
KP2
KP1
Figure 42.
Register 10--AFC Register Comments
* AFC scaling factor:
2 24 x 500 AFC _ SCALING _ FACTOR = ROUND XTAL * * The recommended settings for KI and KP are given below. Note that these settings affect the AFC settling time and AFC accuracy. KI > 6 and KP < 7 Maximum AFC pull-in range: AFC Pull - in Range = MAX _ AFC _ RANGE x 500 Hz * Signals that are within the AFC pull-in range but outside the IF filter bandwidth are attenuated by the IF filter. As a result, the signals may be below the sensitivity point of the receiver, and therefore, not detectable by the AFC. In this case, it is best to scan bandwidths that are equal to the IF filter bandwidth.
Rev. PrI | Page 38 of 44
AE1
M11
KI4
KI3
KI2
KI1
M9
M8
M7
M6
M5
M4
M3
M2
M1
DB0
SB24 DB31 SB23 DB30 SB22 DB29 SB21 DB28 SB20 DB27 SB19 DB26 SB18 DB25 SB17 DB24 SB16 DB23 SB15 DB22 SB14 DB21 SB13 DB20 SB12 DB19 SB11 DB18 SB10 DB17 SB9 SB8 SB7 SB6 SB5 SB4 SB3 SB2
0 0 1 1 SYNC BYTE SEQUENCE
Preliminary Technical Data
REGISTER 11--SYNC WORD DETECT REGISTER
DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 SB1 DB8
Figure 43.
Rev. PrI | Page 39 of 44
MATCHING MT2 MT1 TOLERANCE
05876-041
0 1 0 1 ACCEPT 0 ERRORS ACCEPT 1 ERROR ACCEPT 2 ERRORS ACCEPT 3 ERRORS
MT2 MT1
0 0 1 1 0 1 0 1 12 BITS 16 BITS 20 BITS 24 BITS PL2 PL1 SYNC BYTE LENGTH
DB7 DB6 PL2 PL1 C4 (1) C3 (0) C2 (1) C1 (1) DB5 DB4 DB3 DB2 DB1 DB0
MATCHING TOLERANCE SYNC BYTE LENGTH
CONTROL BITS
ADF7021
ADF7021
REGISTER 12--SWD/THRESHOLD SETUP REGISTER
INT/LOCKPIN MODE LOCK THRESHOLD MODE
Preliminary Technical Data
DATA PACKET LENGTH
CONTROL BITS
DB15
DB14
DB13
DB12
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (0)
C4 (1)
C3 (1)
DATA PACKET LENGTH 0 1 ... 255 INVALID 1 BYTE ... 255 BYTES
INTUPT/LOCK PIN MODE 0 1 2 3 INTUPT PIN LOW INTUPT PIN HIGH AFTER NEXT SYNCWORD INTUPT PIN HIGH AFTER NEXT SYNCWORD FOR DATA_PACKET_LENGTH NUMBER OF BYTES INTUPT PIN HIGH
LOCK THRESHOLD MODE 0 1 2 3 THRESHOLD FREE RUNNING LOCK THRESHOLD AFTER NEXT SYNCWORD LOCK THRESHOLD AFTER NEXT SYNCWORD FOR DATA_PACKET_LENGTH NUMBER OF BYTES LOCK THRESHOLD
C1 (0)
05876-042
LM2
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
Figure 44.
Register 12--SWD/Threshold Setup Register Notes
* Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demod and also locking the AFC and AGC loops.
Rev. PrI | Page 40 of 44
LM1
IL2
IL1
DB0
Preliminary Technical Data
REGISTER 13--3FSK DEMOD REGISTER
3FSK PREAMBLE TIME VALIDATE
ADF7021
HANGUP RECOVERY VITERBI ENABLE VITERBI PATH MEMORY
3FSK CDR THRESHOLD
3FSK/4FSK SLICER THRESHOLD
CONTROL BITS
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
PTV4 DB25
PTV3 DB24
PTV2 DB23
PTV1 DB22
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Figure 45.
REGISTER 14--TEST-DAC REGISTER
PULSE EXTENSION ED PEAK RESPONSE TEST TDAC EN ED LEAK FACTOR
TEST DAC GAIN TEST DAC OFFSET ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
TO16 DB20
TO15 DB19
TO14 DB18
TO13 DB17
TO12 DB16
TO11 DB15
TO10 DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
05876-043
C4 (1)
C3 (1)
C2 (0)
C1 (1)
VM2
VM1
HR1
VE1
VT7
VT6
VT5
VT4
VT3
VT2
VT1
ST7
ST6
ST5
ST4
ST3
ST2
ST1
DB1 C2 (1)
C4 (1)
C3 (1)
ED LEAK FACTOR 0 1 2 3 4 5 6 7 LEAKAGE = 2^-8 2^-9 2^-10 2^-11 2^-12 2^-13 2^-14 2^-15
ED PEAK RESPONSE 0 1 2 3 FULL RESPONSE TO PEAK 0.5 RESPONSE TO PEAK 0.25 RESPONSE TO PEAK 0.125 RESPONSE TO PEAK
TEST DAC GAIN 0 1 ... 15 NO GAIN x 2^1 ... x 2^15
PULSE EXTENSION 0 1 2 3 NO PULSE EXTENSION EXTENDED BY 1 EXTENDED BY 2 EXTENDED BY 3
C1 (0)
05876-044
TG4
TG3
TG2
TG1
TO9
TO8
TO7
TO6
TO5
TO4
TO3
TO2
ER2
ER1
TO1
PE2
PE1
Figure 46.
Register 14--Test-DAC Register Comments
* The demod tuning parameters PULSE_EXTENSION, ED_LEAK_FACTOR, and ED_PEAK_RESPONSE can only be enabled by setting Bits R15_DB[4:7] to 0x9.
Rev. PrI | Page 41 of 44
TE1
EF3
EF2
EF1
DB0
ADF7021
REGISTER 15--TEST MODE REGISTER
CAL OVERRIDE FORCE LD HIGH REG 1 PD
Preliminary Technical Data
ANALOG TEST MODES
PLL TEST MODES
CLK MUX
PFD/CP TEST MODES
- TEST MODES
Tx TEST MODES
Rx TEST MODES
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (1)
C4 (1)
C3 (1)
CAL OVERRIDE 0 1 2 3 AUTO CAL OVERRIDE GAIN OVERRIDE BW OVERRIDE BW AND GAIN PFD/CP TEST MODES 0 1 2 3 4 5 6 7 DEFAULT, NO BLEED (+VE) CONSTANT BLEED (-VE) CONSTANT BLEED (-VE) PULSED BLEED (-VE) PULSE BLD, DELAY UP? CP PUMP UP CP TRI-STATE CP PUMP DN - TEST MODES 0 1 2 3 4 5 6 7 DEFAULT, 3RD ORDER SD, NO DITHER 1ST ORDER SD 2ND ORDER SD DITHER TO FIRST STAGE DITHER TO SECOND STAGE DITHER TO THIRD STAGE DITHER x 8 DITHER x 32 Tx TEST MODES 0 1 2 3 4 5 6 NORMAL OPERATION Tx CARRIER ONLY Tx +VE TONE ONLY Tx -VE TONE ONLY Tx "1010" PATTERN Tx PN9 DATA, AT PROGRAMMED RATE Tx SYNC BYTE REPEATEDLY Rx TEST MODES PLL TEST MODES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NORMAL OPERATION R DIV N DIV RCNTR/2 ON MUXOUT NCNTR/2 ON MUXOUT ACNTR TO MUXOUT PFD PUMP UP TO MUXOUT PFD PUMP DN TO MUXOUT SDATA TO MUXOUT (OR SREAD?) ANALOG LOCK DETECT ON MUXOUT END OF COARSE CAL ON MUXOUT END OF FINE CAL ON MUXOUT FORCE NEW PRESCALER CONFIG. FOR ALL N TEST MUX SELECTS DATA LOCK DETECT PRECISION NEG PD POLARITY-*NOT SUPPORTED* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NORMAL SCLK, SDATA -> I, Q REVERSE I, Q DDT SLICER ON RxDATA T/4 SLICER ON RxDATA 3FSK SLICER ON RxDATA I, Q TO Rx CLK, RxDATA SDATA TO CDR ADDITIONAL FILTERING ON I, Q ENABLE REG 14 DEMOD PARAMETERS POWER DOWN DDT AND ED IN T/4 MODE ENVELOPE DETECTOR WATCHDOG DISABLED 3FSK PREMABLE DETECT ON RxDATA PROHIBIT CALACTIVE FORCE CALACTIVE ENABLE DEMOD DURING CAL
REG1 PD 0 1 NORMAL PWR DWN FORCE LD HIGH 0 1 NORMAL FORCE ANALOG TEST MODES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BAND GAP VOLTGE 40A CURRENT FROM REG4 FILTER I CHANNEL: STAGE 1 FILTER I CHANNEL: STAGE 2 FILTER I CHANNEL: STAGE 1 FILTER Q CHANNEL: STAGE 1 FILTER Q CHANNEL: STAGE 2 FILTER Q CHANNEL: STAGE 1 ADC REFERENCE VOLTAGE BIAS CURRENT FROM RSSI 5A FILTER COARSE CAL OSCILLATOR O/P ANALOG RSSI I CHANNEL OSET LOOP +VE FBACK V (I CH) SUMMED O/P OF RSSI RECTIFIER+ SUMMED O/P OF RSSI RECTIFIER- BIAS CURRENT FROM BB FILTER
CLK MUXES 0 1 2 3 4 5 6 7 NORMAL, NO OUTPUT DEMOD_CLK CDR_CLK SEQ_CLK BB_OFFSET CLK SIGMA_DELTA CLK ADC_CLK Tx/Rx CLK
C1 (1)
AM3
AM2
AM4
AM1
CM3
CM2
CM1
CO2
CO1
PM4
PM3
PM2
PM1
TM3
TM2
TM1
RD1
PC3
PC2
PC1
SD3
SD2
SD1
RT2
RT4
RT3
FH1
RT1
DB0
Figure 47.
Rev. PrI | Page 42 of 44
05876-045
Preliminary Technical Data
Using the Test DAC on the ADF7021 to Implement Analog FM DEMOD and Measuring SNR
The test DAC allows the output of the postdemodulator filter for both the linear and correlator/demodulators (Figure 21 and Figure 22) to be viewed externally. It takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order error feedback - converter. The output can be viewed on the XCLKOUT pin. This signal, when IF filtered appropriately, can then be used to * Monitor the signals at the FSK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams can also be constructed of the received bit stream to measure the received signal quality. Provide analog FM demodulation.
ADF7021
While the correlators and filters are clocked by DEMOD_CLK, CDR_CLK clocks the test DAC. Note that although the test DAC functions in regular user mode, the best performance is achieved when the CDR_CLK is increased up to or above the frequency of DEMOD_CLK. The CDR block does not function when this condition exists. Programming Register 14 enables the test DAC. Both the linear and correlator/demodulator outputs can be multiplexed into the DAC. Register 14 allows a fixed offset term to be removed from the signal (to remove the IF component in the ddt case). It also has a signal gain term to allow the usage of the maximum dynamic range of the DAC.
*
Rev. PrI | Page 43 of 44
ADF7021 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
Preliminary Technical Data
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
4.25 4.10 SQ 3.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 x 7 mm Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADF7021BCPZ1 EVAL-ADF70XXMB EVAL-ADF70XXMB2 EVAL-ADF7021DB2 EVAL-ADF7021DB3
1
Temperature Range -40C to +85C
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Control Mother Board Evaluation Platform 860 MHz to 870 MHz Daughter Board 431 MHz to 470 MHz Daughter Board
Package Option CP-48-3
Z = Pb-free part.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05876-0-9/06(PrI)
Rev. PrI | Page 44 of 44

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